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authorazidar2015-05-20 01:35:15 -0700
committerazidar2015-05-20 01:35:15 -0700
commited04a9040f20c5e04880a18ec036c1a641443c50 (patch)
treecb9cd4db719484c0a8ea52054915841bc8e0eb14 /src
parent92e7da031a14df41ee0cab13a4a63b472fbdb5e1 (diff)
Added Pad pass to flo.stanza, which pads widths to make := and primops strict. Have not tested this
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/compilers.stanza1
-rw-r--r--src/main/stanza/flo.stanza61
-rw-r--r--src/main/stanza/passes.stanza1
3 files changed, 59 insertions, 4 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 901f6100..762ed9a8 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -27,6 +27,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
ExpandIndexedConnects()
ExpandWhens()
InferWidths()
+ Pad()
Inline()
SplitExp()
ToRealIR()
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 4bab7025..3e39c526 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -3,15 +3,70 @@ defpackage firrtl/flo :
import verse
import firrtl/ir-utils
import firrtl/ir2
+ import firrtl/passes
+
+;========== Pad Widths ==================
+
+public defstruct Pad <: Pass
+public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths
+public defmethod name (b:Pad) -> String : "Pad Widths"
+
+defn int-width! (t:Type) -> Int :
+ match(width!(t)) :
+ (w:IntWidth) : width(w)
+ (w) : error("Non-int width")
+
+defn set-width (desired:Int,t:Type) -> Type :
+ match(t) :
+ (t:UIntType) : UIntType(IntWidth(desired))
+ (t:SIntType) : SIntType(IntWidth(desired))
+ (t) : error("Non-ground type")
+
+defn pad-widths-e (desired:Int,e:Expression) -> Expression :
+ match(e) :
+ (e:DoPrim) :
+ println(e)
+ val e* = map(pad-widths-e{desired,_},e)
+ val i = int-width!(type(e*))
+ if i > desired : error("Cannot pad a larger width to a smaller width")
+ else if i == desired : e*
+ else : DoPrim(PAD-OP,list(e*),list(),set-width(desired,type(e*)))
+ (e:WRef|WSubfield|WIndex) :
+ println(e)
+ val i = int-width!(type(e))
+ if i > desired : error("Cannot pad a larger width to a smaller width")
+ else if i == desired : e
+ else : DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e)))
+ (e:UIntValue) :
+ val i = int-width!(type(e))
+ if i > desired : error("Cannot pad a larger width to a smaller width")
+ else : UIntValue(value(e),IntWidth(desired))
+ (e:SIntValue) :
+ val i = int-width!(type(e))
+ if i > desired : error("Cannot pad a larger width to a smaller width")
+ else : SIntValue(value(e),IntWidth(desired))
+ (e) : error(to-string $ e)
+
+defn pad-widths-s (s:Stmt) -> Stmt :
+ match(map(pad-widths-s,s)) :
+ (s:Connect) :
+ val i = int-width!(type(loc(s)))
+ val exp* = pad-widths-e(i,exp(s))
+ Connect(info(s),loc(s),exp*)
+ (s) : s
+
+public defn pad-widths (c:Circuit) -> Circuit :
+ Circuit{info(c),_,main(c)} $
+ for m in modules(c) map :
+ Module(info(m),name(m),ports(m),pad-widths-s(body(m)))
+
+;============= Flo Backend ================
public defstruct Flo <: Pass :
file : String
public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{file(b),_}
public defmethod name (b:Flo) -> String : "To Flo"
-;============= FLO PRINTER ======================================
-; Emit
-
defn is-sint? (arg:Expression) -> True|False : type(arg) typeof SIntType
defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4439e069..b6926a7b 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1586,7 +1586,6 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> :
println-debug("==== SOLUTIONS TABLE (Post backsolve) ====")
for x in b do : println-debug(x)
println-debug("=========================")
-
b
public defn width! (t:Type) -> Width :