sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2021-02-25	Emit space after 'if' for all Verilog conditional synchronous assignments (#2...	Albert Magyar
2021-02-17	ExpandWhens: ensure that statement names are maintained (#2082)	Kevin Laeufer
2021-02-17	Allow Side Effecting Statement to have Names (#2057)	Kevin Laeufer
2021-02-16	Add MustDeduplicateTransform	Jack Koenig
2021-02-16	Add DiGraph factory method and prettyTree	Jack Koenig
2021-02-03	IR: turn some IR nodes into data classes (#2071)	Kevin Laeufer
2021-02-01	Suport ir.SubAccess in Utils.splitRef (#2021)	Schuyler Eldridge
2021-02-01	Deprecate ToWorkingIR (#2028)	Schuyler Eldridge
2021-02-01	ConstantPropagation: make RemoveValidIf an optional dependency (#2027)	Kevin Laeufer
2021-01-28	Stop padding multiply and divide ops (#2058)	Jack Koenig
2021-01-26	Fix post-merge publishing (#2055)	Jack Koenig
2021-01-20	Cleanup some warnings (#2032)	Jack Koenig
2021-01-20	Add --dont-fold option to disable folding prim ops (#2040)	Schuyler Eldridge
2021-01-19	Restore scalafmt CI check (#2047)	Jack Koenig
2021-01-19	smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)	Kevin Laeufer
2020-12-15	Improve performance of LowerTypes renaming (#2024)	Jack Koenig
2020-12-11	fix scaladoc for ReferenceTarget (#2014)	Megan Wachs
2020-12-10	Add newline in the end of LoFIRRTL file (#2015)	XinJun Ma
2020-12-02	smt: add support for uninterpreted ext modules (#1994)	Kevin Laeufer
2020-12-02	Fix subaccess (#1984)	Jiuyang Liu
2020-11-30	Add SortModules Transform (#1905)	Schuyler Eldridge
2020-11-23	add weak and strong to Utils.v_keywords (#1983)	Tim Snyder
2020-11-17	Make MultiTargetAnnotation.targets a def (#1969)	Jack Koenig
2020-11-16	make LazyLogging log to console by default. (#1961)	Jiuyang Liu
2020-11-12	Fix RemoveWires handling of invalidated non-UInt wires (#1949)	Jack Koenig
2020-11-11	smt: add support for write-first memories (#1948)	Kevin Laeufer
2020-11-10	Fix SMT Memory Bug (#1942)	Kevin Laeufer
2020-11-10	Refactor emiter (#1879)	Jiuyang Liu
2020-11-09	smt: ensure that all signals have a unique name (#1943)	Kevin Laeufer
2020-11-07	-full64 is required to detect VCS. (#1930)	Jiuyang Liu
2020-11-04	Remove caching from RenameMap (#1938)	Jack Koenig
2020-10-26	fix for LoweringCompilersSpec.	Jiuyang liu
2020-10-26	bug fix for VerilogPrep using wrong type.	Jiuyang liu
2020-10-26	fix a test not detecting verilog name conflicts.	Jiuyang liu
2020-10-13	Make {Stage, FirrtlStage}.run protected (#1926)	Schuyler Eldridge
2020-10-01	Fix "fix" for negative literals > 32 bits	Jack Koenig
2020-09-30	Add test for chaining RW-port rdata as wdata of another mem	Albert Magyar
2020-09-30	Handle case where rdata of mem RW port split to R+W ports drives another mem	Albert Magyar
2020-09-30	Speed up writing CustomFileEmission with buffering (#1906)	Jack Koenig
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-09-15	Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)	Jack Koenig
2020-09-14	Hit connect case in DedupModuleTests (#1716)	Schuyler Eldridge
2020-09-09	Make StageOption Unserializable (#1891)	Jack Koenig
2020-09-09	Loosen inlining restrictions (#1882)	Albert Chen
2020-09-06	Add --pretty:no-expr-inlining to prevent expression inlining (#1869)	Jack Koenig
2020-09-06	Support binary files in CustomFileEmission (#1887)	Jack Koenig
2020-09-05	Better error messages for unserializable annotations (#1885)	Jack Koenig
2020-09-04	Add test for mem port clock legalization	Albert Magyar
2020-09-04	Legalize memory port clocks	Albert Magyar
2020-09-01	InlineBooleanExpressions: test DontTouch (#1880)	Albert Chen