diff options
| author | Jack Koenig | 2020-11-04 15:55:12 -0800 |
|---|---|---|
| committer | GitHub | 2020-11-04 23:55:12 +0000 |
| commit | 8d765c981063b6e44b4473aba2121217e6466f02 (patch) | |
| tree | c94e80ed60f9c2872ce1784c8257e65c8b5055c9 /src | |
| parent | 64e1ea1e8e4667649b648d7156027c450e24c788 (diff) | |
Remove caching from RenameMap (#1938)
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/RenameMap.scala | 188 |
1 files changed, 88 insertions, 100 deletions
diff --git a/src/main/scala/firrtl/RenameMap.scala b/src/main/scala/firrtl/RenameMap.scala index c32823b2..df98f72f 100644 --- a/src/main/scala/firrtl/RenameMap.scala +++ b/src/main/scala/firrtl/RenameMap.scala @@ -190,10 +190,6 @@ final class RenameMap private ( */ private val sensitivity = mutable.HashSet[IsComponent]() - /** Caches results of recursiveGet. Is cleared any time a new rename target is added - */ - private val getCache = mutable.HashMap[CompleteTarget, Seq[CompleteTarget]]() - /** Caches results of referenceGet. Is cleared any time a new rename target is added */ private val traverseTokensCache = mutable.HashMap[ReferenceTarget, Option[Seq[IsComponent]]]() @@ -505,111 +501,104 @@ final class RenameMap private ( * @return Renamed targets */ private def recursiveGet(errors: mutable.ArrayBuffer[String])(key: CompleteTarget): Seq[CompleteTarget] = { - if (getCache.contains(key)) { - getCache(key) - } else { + // rename just the component portion; path/ref/component for ReferenceTargets or path/instance for InstanceTargets + val componentRename = key match { + case t: CircuitTarget => None + case t: ModuleTarget => None + case t: InstanceTarget => instanceGet(errors)(t) + case ref: ReferenceTarget if ref.isLocal => referenceGet(errors)(ref) + case ref @ ReferenceTarget(c, m, p, r, t) => + val (Instance(inst), OfModule(ofMod)) = p.last + val refGet = referenceGet(errors)(ref) + if (refGet.isDefined) { + refGet + } else { + val parent = InstanceTarget(c, m, p.dropRight(1), inst, ofMod) + instanceGet(errors)(parent).map(_.map(ref.setPathTarget(_))) + } + } - // rename just the component portion; path/ref/component for ReferenceTargets or path/instance for InstanceTargets - val componentRename = key match { - case t: CircuitTarget => None - case t: ModuleTarget => None - case t: InstanceTarget => instanceGet(errors)(t) - case ref: ReferenceTarget if ref.isLocal => referenceGet(errors)(ref) - case ref @ ReferenceTarget(c, m, p, r, t) => - val (Instance(inst), OfModule(ofMod)) = p.last - val refGet = referenceGet(errors)(ref) - if (refGet.isDefined) { - refGet - } else { - val parent = InstanceTarget(c, m, p.dropRight(1), inst, ofMod) - instanceGet(errors)(parent).map(_.map(ref.setPathTarget(_))) - } - } + // if no component rename was found, look for Module renames; root module/OfModules in path + val moduleRename = if (componentRename.isDefined) { + componentRename + } else { + key match { + case t: CircuitTarget => None + case t: ModuleTarget => moduleGet(errors)(t) + case t: IsComponent => + ofModuleGet(errors)(t) match { + case AbsoluteOfModule(absolute) => + t match { + case ref: ReferenceTarget => + Some(Seq(ref.copy(circuit = absolute.circuit, module = absolute.module, path = absolute.asPath))) + case inst: InstanceTarget => Some(Seq(absolute)) + } + case RenamedOfModules(children) => + // rename the root module and set the new path + val modTarget = ModuleTarget(t.circuit, t.module) + val result = moduleGet(errors)(modTarget).getOrElse(Seq(modTarget)).map { mod => + val newPath = mod.asPath ++ children - // if no component rename was found, look for Module renames; root module/OfModules in path - val moduleRename = if (componentRename.isDefined) { - componentRename - } else { - key match { - case t: CircuitTarget => None - case t: ModuleTarget => moduleGet(errors)(t) - case t: IsComponent => - ofModuleGet(errors)(t) match { - case AbsoluteOfModule(absolute) => t match { - case ref: ReferenceTarget => - Some(Seq(ref.copy(circuit = absolute.circuit, module = absolute.module, path = absolute.asPath))) - case inst: InstanceTarget => Some(Seq(absolute)) + case ref: ReferenceTarget => ref.copy(circuit = mod.circuit, module = mod.module, path = newPath) + case inst: InstanceTarget => + val (Instance(newInst), OfModule(newOfMod)) = newPath.last + inst.copy( + circuit = mod.circuit, + module = mod.module, + path = newPath.dropRight(1), + instance = newInst, + ofModule = newOfMod + ) } - case RenamedOfModules(children) => - // rename the root module and set the new path - val modTarget = ModuleTarget(t.circuit, t.module) - val result = moduleGet(errors)(modTarget).getOrElse(Seq(modTarget)).map { mod => - val newPath = mod.asPath ++ children - - t match { - case ref: ReferenceTarget => ref.copy(circuit = mod.circuit, module = mod.module, path = newPath) - case inst: InstanceTarget => - val (Instance(newInst), OfModule(newOfMod)) = newPath.last - inst.copy( - circuit = mod.circuit, - module = mod.module, - path = newPath.dropRight(1), - instance = newInst, - ofModule = newOfMod - ) - } - } - Some(result) - case DeletedOfModule => Some(Nil) - case NoOfModuleRenames => - val modTarget = ModuleTarget(t.circuit, t.module) - val children = t.asPath - moduleGet(errors)(modTarget).map(_.map { mod => - val newPath = mod.asPath ++ children - - t match { - case ref: ReferenceTarget => ref.copy(circuit = mod.circuit, module = mod.module, path = newPath) - case inst: InstanceTarget => - val (Instance(newInst), OfModule(newOfMod)) = newPath.last - inst.copy( - circuit = mod.circuit, - module = mod.module, - path = newPath.dropRight(1), - instance = newInst, - ofModule = newOfMod - ) - } - }) - } - } - } + } + Some(result) + case DeletedOfModule => Some(Nil) + case NoOfModuleRenames => + val modTarget = ModuleTarget(t.circuit, t.module) + val children = t.asPath + moduleGet(errors)(modTarget).map(_.map { mod => + val newPath = mod.asPath ++ children - // if no module renames were found, look for circuit renames; - val circuitRename = if (moduleRename.isDefined) { - moduleRename.get - } else { - key match { - case t: CircuitTarget => circuitGet(errors)(t) - case t: ModuleTarget => - circuitGet(errors)(CircuitTarget(t.circuit)).map { - case CircuitTarget(c) => t.copy(circuit = c) - } - case t: IsComponent => - circuitGet(errors)(CircuitTarget(t.circuit)).map { - case CircuitTarget(c) => t match { - case ref: ReferenceTarget => ref.copy(circuit = c) - case inst: InstanceTarget => inst.copy(circuit = c) + case ref: ReferenceTarget => ref.copy(circuit = mod.circuit, module = mod.module, path = newPath) + case inst: InstanceTarget => + val (Instance(newInst), OfModule(newOfMod)) = newPath.last + inst.copy( + circuit = mod.circuit, + module = mod.module, + path = newPath.dropRight(1), + instance = newInst, + ofModule = newOfMod + ) } - } - } + }) + } } + } - // Cache result - getCache(key) = circuitRename - circuitRename + // if no module renames were found, look for circuit renames; + val circuitRename = if (moduleRename.isDefined) { + moduleRename.get + } else { + key match { + case t: CircuitTarget => circuitGet(errors)(t) + case t: ModuleTarget => + circuitGet(errors)(CircuitTarget(t.circuit)).map { + case CircuitTarget(c) => t.copy(circuit = c) + } + case t: IsComponent => + circuitGet(errors)(CircuitTarget(t.circuit)).map { + case CircuitTarget(c) => + t match { + case ref: ReferenceTarget => ref.copy(circuit = c) + case inst: InstanceTarget => inst.copy(circuit = c) + } + } + } } + + circuitRename } /** Fully rename `from` to `tos` @@ -621,7 +610,6 @@ final class RenameMap private ( val existing = underlying.getOrElse(from, Vector.empty) val updated = (existing ++ tos).distinct underlying(from) = updated - getCache.clear() traverseTokensCache.clear() traverseHierarchyCache.clear() traverseLeftCache.clear() |
