diff options
| author | Megan Wachs | 2020-12-11 12:09:03 -0800 |
|---|---|---|
| committer | GitHub | 2020-12-11 20:09:03 +0000 |
| commit | 93869ccec89aa9739b6fe9f0e3bd62ae8cf155cd (patch) | |
| tree | d3d7a2492b764b2c929890b66a5f954eec4b547e /src | |
| parent | 5fb8845fedb39ad73a70e5df372cdd7ab69b89f5 (diff) | |
fix scaladoc for ReferenceTarget (#2014)
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/annotations/Target.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/annotations/Target.scala b/src/main/scala/firrtl/annotations/Target.scala index 137d070e..8e84a269 100644 --- a/src/main/scala/firrtl/annotations/Target.scala +++ b/src/main/scala/firrtl/annotations/Target.scala @@ -612,7 +612,7 @@ case class ModuleTarget(circuit: String, module: String) extends IsModule { } /** Target pointing to a declared named component in a [[firrtl.ir.DefModule]] - * This includes: [[firrtl.ir.Port]], [[firrtl.ir.DefWire]], [[firrtl.ir.DefRegister]], [[firrtl.ir.DefInstance]], + * This includes: [[firrtl.ir.Port]], [[firrtl.ir.DefWire]], [[firrtl.ir.DefRegister]], * [[firrtl.ir.DefMemory]], [[firrtl.ir.DefNode]] * @param circuit Name of the encapsulating circuit * @param module Name of the root module of this reference |