| Age | Commit message (Expand) | Author |
|---|
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-06-02 | turn off eliminate-temps until improved | jackbackrack |
| 2015-06-02 | merge + fix trim to use correct bits operands | jackbackrack |
| 2015-05-29 | fix concat, as-sint, turn off temp-elimination | jackbackrack |
| 2015-05-29 | Fixed bugs in when-coverage pass. Works but has not been thoroughly tested | azidar |
| 2015-05-29 | Added new stanza | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-21 | fix pad/trim pass and fix bug in bits-select width inference | jackbackrack |
| 2015-05-21 | Added pad pass, used for flo backend | azidar |
| 2015-05-20 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-05-20 | fix writeport emission for flo | jackbackrack |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Merge pull request #8 from jackbackrack/master | Adam Izraelevitz |
| 2015-05-19 | merge | jackbackrack |
| 2015-05-19 | get flo backend running again with no pads and generic operators | jackbackrack |
| 2015-05-19 | Added support for non-inlined modules in verilog backend | azidar |
| 2015-05-18 | get coercion running for flo backend and disable negative lit check | jackbackrack |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-14 | merge | jackbackrack |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar |
| 2015-05-07 | do signed padding as well | jackbackrack |
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check t... | azidar |
| 2015-05-04 | merge | jackbackrack |
| 2015-05-04 | Added new stanza | azidar |
| 2015-05-04 | Fixed bug where instance types were not lowered | azidar |
| 2015-05-04 | merge | jackbackrack |
| 2015-05-04 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-05-04 | Updated stuff | azidar |
| 2015-05-04 | add reduction operators | jackbackrack |
| 2015-05-04 | Merge pull request #6 from jackbackrack/master | Adam Izraelevitz |
| 2015-05-04 | Added a few more error checks. Not tested yet. Fixed bug in pad type inference | azidar |
| 2015-05-04 | merge | jackbackrack |
| 2015-05-04 | Fixed change where type of mux-ss was incorrect | azidar |
| 2015-05-02 | merge | jackbackrack |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
| 2015-05-02 | Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn... | azidar |
| 2015-05-01 | add arsh refs | jackbackrack |
| 2015-05-01 | Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one) | azidar |
| 2015-05-01 | Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp... | azidar |
| 2015-05-01 | merge | jackbackrack |
