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This will allow chiseltest to save
the hash code to disk for the purpose
of caching simulation binaries.
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
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* Restore parsed MultiInfo structure in firrtl parser
* Change erroneous expected output in InfoSpec test
FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact
* Fix typo in comment
* Add unit tests for file locator parsing
* Fix syntax issues and typos
* More redundant braces removed
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: include firrtl statement names in SMT and btor2 output
* smt: remove println
* smt: make tests run again and fix stale ones
Apparently `private` classes aren't found by th sbt test runner.
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Add a new option to the FIRRTL compiler, "--start-from = <form>". If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form. It will then skip unnecessary
passes given this information.
E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).
To implement this, a CurrentFirrtlStateAnnotation is added. Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add Protocol Buffer emission export
This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.
Fixes #1696.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add Protocol Buffer emission export
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* make PresetRegAnnotation public
this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
need to be initialized at the beginning of simulation
(e.g., for formal verification)
- to support preset registers in treadle
* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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Add a compiler/emitter that can target minimal high form. This will
produce output that only has CHIRRTL constructs removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* ReplaceMemMacros: add target rename test case
* ReplaceMemMacros: rename references to instances
* fix renaming for deduped mems
* use grouped DummyAnnos to preserve order
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* run scalafmt
* flatten targets
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add more inline renaming test cases
* InlineInstances: fix renaming for local targets
* run scalafmt
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.
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* add os-lib to dependency.
* use os-lib in Z3ModelChecker
* fix for review by Kevin.
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This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.
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* Implement MFC-style source locator compression
* Fix formatting issues
* Fix emitting empty FileInfo if the firrtl doesn't have one
* Remove '.scala' requirement in FileInfo parsing regex
* Handle parsing of FileInfos with no line/col nums
* Split FileInfos only if they match
This should fix any issues with FileInfos that do not use the "file line:col"
format, and allow any valid firrtl using these info comments to compile.
* Add unit tests for locator compression
* Move InfoTests to InfoSpec class
* Fix existing unit tests with fileinfo comments
* Add unit tests to ignore the algorithm's own output
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* remove all deprecations, switch to new API.
* Add MemLibOutConfigFileAnnotation to replace ConfWriter.
* Inline CreateMemoryAnnotations in ReplSeqMem.
* Dont use ConfWriter anymore.
* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.
* Fix for review.
0. Since DependencyAPI only initiate transform only once, ListBuffer is
dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
MemLibOutConfigFileAnnotation also extends from which now.
* Use two annotations converting and storing DefMemory.
0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform
* Fix for review.
0. replace AnnotatedMemoriesCollectorAnnotation with immutable
AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.
* private functions in ReplaceMemMacros transform.
* scalafmt
* remove ConfWriter API.
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* Fixes #2173
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Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
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To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update test to include both 'old' and 'new' read-under-write values
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* Emit readwrite ports, if applicable
* Does not change VerilogMemDelays -> no effect on default flow
* Use more single-line declare-and-assign statements for mem wires
* Update error messages for too-complex memories in VerilogEmitter
* Run scalafmt on VerilogEmitter
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This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.
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CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add --no-constant-propagation to disable constant propagation
* add test
* deprecate DisableFold.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Fix bug in zero-width memory removal
Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories. Previously,
only read ports were correctly handled.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix bug in zero-width memory removal
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This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.
This behavior matches that of Chisel (which directly emits the 0 - x
already).
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Previously, InlineCasts could inline complex (ie. non-cast) Expressions
into other complex Expressions. Now it will only inline so long as there
no more than 1 complex Expression in the current nested Expression.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:
input a: UInt<4>
input b: SInt<1>
output o: UInt<5>
o <= dshl(a, asUInt(cvt(b)))
Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.
This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.
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Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.
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The flow of a LHS SubAccess node may still be SourceFlow if the type of
the Vec element has a flip. Tweak the logic of CSESubAccesses to check
every Expression flow while recursing instead of just the flow of the
final SubAccess.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This PR adds a new annotation allowing inline loading for memory files
in Verilog code.
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This finally removes all randomization code from the transition
system conversion and into a separate pass using DefRandom nodes.
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* SMT: memory port inout fields cannot be used as RHS expressions
* smt: add end2end check for read enable modelling
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With this PR the smt backend now supports memories
with more than two write ports and the conservative
memory modelling can be selectively turned off with
a new annotation.
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Fixes n^2 performance problem when dynamically indexing Vecs of
aggregate types.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Bumping Scala minor version but not bumping CI guards on the version
causes tests to no longer run. Change to using startsWith(...) so that
minor version bumps won't cause issues in the future.
Also run ScalaFmt
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* firrtl: add optional statement labels for stop, printf, assert, assume and cover
* test: parsing of statement labels
* ir: ensure that name is properly retained
* SymbolTable: add support for labled statements
* test: parsing statement labels
* test: lower types name collisions with named statements
* ignore empty names
* Inline: deal with named and unnamed statements
* RemoveWires: treat stop, printf and verification statements as "others"
* test: fix InlineInstance tests
* DeadCodeEliminations: statements are now als declarations
* CheckHighForm: ensure that statement names are not used as references
* CheckSpec: throw error if statement name collides
* add pass to automatically add missing statement names
* check: make sure that two statements cannot have the same name
* stmtLabel -> stmtName
* scalafmt
* add statement names to spec
* spec: meta data -> metadata
* EnsureStatementNames: explain naming algorithm
* remove returns
* better namespace use
* ir: add CanBeReferenced trait
* ir: add newline as jack requested
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This enables marking modules as "must deduplicate". If modules marked as
such do not deduplicate, the transform will create error reports and
make suggestions as to why deduplication failed.
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* Deprecate firrtl.passes.ToWorkingIR
Deprecate ToWorkingIR as it is now an identity transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Deprecate firrtl.stage.Forms.WorkingIR
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Switch from Forms.WorkingIR to Forms.MinimalHighForm
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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