aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests
AgeCommit message (Expand)Author
2019-11-14Add test with Transform inside objectSchuyler Eldridge
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-19Faster inline renaming (#1184)Albert Chen
2019-09-16Rename gender to flowSchuyler Eldridge
2019-09-12update inline transform and testcasesAbert Chen
2019-09-05clean up spacing in inline testabejgonzalez
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
2019-08-07Add tests on RemoveReset of invalid initsSchuyler Eldridge
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-08-07DRY check chirrtl (#1148)Albert Magyar
2019-08-05Add FileUtilsSpecSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-08-01Followup to PR #1142chick
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
2019-07-21Fix RenameMap chaining (#1126)Albert Chen
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
2019-07-19Fix renaming of annotations with paths (#967)Albert Chen
2019-07-15Add type aliases for dependenciesSchuyler Eldridge
2019-07-11Change Dependency API to Class[_ <: A]Schuyler Eldridge
2019-07-08Fix typo (#1114)Leway Colin
2019-07-03Add PhaseManager testsSchuyler Eldridge
2019-07-02Make sure directory exist before writing (#1110)Leway Colin
2019-06-28Remove deprecated ComponentName from CombinationalPath annotation (#1107)Albert Magyar
2019-06-28Add Test for AddDefaults phase (#1106)Leway Colin
2019-05-24Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)Jack Koenig
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25Add tests for Annotations/Options refactorSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-04-11LowerTypesSpec: additional unit test (#1071)edwardcwang
2019-03-29Faster reg constprop (#1067)Albert Magyar
2019-03-26Add test for DCE of printf and stopAndrew Waterman
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-06 18:28:32 +0000