sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-02-13	Constant prop binary PrimOps with matching arguments	Albert Magyar
2020-02-13	Add tests for (Un)?reachable InstanceGraph Methods	Schuyler Eldridge
2020-02-12	Add test of RenameMap not recording same rename	Schuyler Eldridge
2020-02-12	Add test of RenameMap self-renaming	Schuyler Eldridge
2020-02-12	Repl seq mem renaming (#1286)	Jack Koenig
2020-02-11	Add InstanceGraph.staticInstanceCount tests	Schuyler Eldridge
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
2020-02-12	Fixing lint error: x + -1 (#1374)	Adam Izraelevitz
2020-02-10	Test EliminateTargetPaths ModuleTarget anno duping	Schuyler Eldridge
2020-02-07	Add extra 'de-optimization' opportunity for register const prop test	Albert Magyar
2020-02-06	Better register const prop through speculative de-optimization	Albert Magyar
2020-02-06	Add constant prop to async regs (#1355)	Adam Izraelevitz
2020-02-06	[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)	Albert Magyar
2020-02-06	Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)	Albert Magyar
2020-01-15	Verilog emitter transform InlineBitExtractions (#1296)	John Ingalls
2020-01-15	improve the tail ir usability. (#1241)	Sequencer
2020-01-15	Filter ResolvePaths in EliminateTargetPaths (#1310)	Schuyler Eldridge
2020-01-10	Change LoggerState.globalLevel to Warn (#1307)	Jim Lawson
2020-01-09	Dedup PassTests, add NoCircuitDedupAnnotations (#1302)	Schuyler Eldridge
2020-01-07	Remove printlns from tests	Jack Koenig
2020-01-07	Switch compileFirrtlTest from Driver to FirrtlStage	Jack Koenig
2020-01-07	Redirect testing shell commands to logger	Jack Koenig
2020-01-07	Fix literals cast to Clocks in Print and Stop	Jack Koenig
2020-01-07	Remove unnecessary $signed casts for PrimOps in Verilog Emitter	Jack Koenig
2020-01-07	Remove unnecessary casts in Constant Propagation	Jack Koenig
2020-01-06	Verilog emitter transform InlineNots (#1270)	John Ingalls
2019-12-30	Respect last connect semantics in InferResets	Jack Koenig
2019-11-29	Remove scala-logging fully in favor of our own logger	Jack Koenig
2019-11-19	Error when blackboxing memories with unsupported masking (#1238)	Abraham Gonzalez
2019-11-14	Add test with Transform inside object	Schuyler Eldridge
2019-11-07	Add check for multiple sources for same wiring pin (#1191)	Jack Koenig
2019-11-05	Move CheckResets after CheckCombLoops (#1224)	Jack Koenig
2019-11-04	Merge branch 'master' into serialization-utils	Jack Koenig
2019-11-04	Ignore extmodule instances in Flatten (#1218)	Albert Magyar
2019-11-04	Add explicit EOF to top-level parser rule (#1217)	Albert Magyar
2019-10-31	Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS	Jack Koenig
2019-10-30	Add some simple tests to demonstrate how to provide type hints	David Biancolin
2019-10-29	Change findInstancesInHierarchy to return implicit top instance	Albert Magyar
2019-10-22	Add Register Updates/else-if Verilog Emitter tests	Schuyler Eldridge
2019-10-21	Add tests for memories with latency >1, toggling enables	Albert Magyar
2019-10-21	Add library for streamlined Verilog execution tests	Albert Magyar
2019-10-21	Add test for #1179: comb-loops from VerilogMemDelays	Albert Magyar
2019-10-18	Upstream intervals (#870)	Adam Izraelevitz
2019-10-08	Add test for TopWiringTransform idempotency	Schuyler Eldridge
2019-09-30	Implement read-first memories in VerilogMemDelays	Albert Magyar
2019-09-30	Improve read-under-write parameter support	Albert Magyar
2019-09-19	Faster inline renaming (#1184)	Albert Chen
2019-09-16	Rename gender to flow	Schuyler Eldridge
2019-09-12	update inline transform and testcases	Abert Chen
2019-09-05	clean up spacing in inline test	abejgonzalez