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AgeCommit message (Expand)Author
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
2019-08-07Add tests on RemoveReset of invalid initsSchuyler Eldridge
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-08-07DRY check chirrtl (#1148)Albert Magyar
2019-08-05Add FileUtilsSpecSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-08-01Followup to PR #1142chick
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
2019-07-21Fix RenameMap chaining (#1126)Albert Chen
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
2019-07-19Fix renaming of annotations with paths (#967)Albert Chen
2019-07-15Add type aliases for dependenciesSchuyler Eldridge
2019-07-11Change Dependency API to Class[_ <: A]Schuyler Eldridge
2019-07-08Fix typo (#1114)Leway Colin
2019-07-03Add PhaseManager testsSchuyler Eldridge
2019-07-02Make sure directory exist before writing (#1110)Leway Colin
2019-06-28Remove deprecated ComponentName from CombinationalPath annotation (#1107)Albert Magyar
2019-06-28Add Test for AddDefaults phase (#1106)Leway Colin
2019-05-24Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)Jack Koenig
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25Add tests for Annotations/Options refactorSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-04-11LowerTypesSpec: additional unit test (#1071)edwardcwang
2019-03-29Faster reg constprop (#1067)Albert Magyar
2019-03-26Add test for DCE of printf and stopAndrew Waterman
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
2019-03-18Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation (#1056)Jim Lawson
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
2019-02-28[ExpandWhens] Don't create nodes to hold Muxes with >0 void cases (#1039)Albert Magyar
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
2019-02-27Create a simple generic GraphViz renderer for DiGraph (#1034)Chick Markley
2019-02-25Run CheckHighForm after all non-emitter transforms in firrtl tests (#548)Jack Koenig
2019-02-25Detect and error on registers with flip in type (#1031)Albert Magyar
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
2019-02-22Stop reporting exceptions in custom transformations as internal errors (#867)Jack Koenig
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21No time left for you - quickly rename deep bundles still occasionally fails. ...Jim Lawson
2019-02-21Prevent Flatten from stripping all annotations (#1024)Schuyler Eldridge
2019-02-21Correctly handle dots in loaded memory paths (#984)Nick Hynes
2019-02-20Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles...Jim Lawson
2019-02-14Asynchronous Reset (#1011)Jack Koenig
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
2019-02-05Add RemoveValidIf to -X mverilogSchuyler Eldridge
2019-02-05Add "mverilog" and "sverilog" DriverSpec testsSchuyler Eldridge
2019-02-05Add "mverilog" Compiler Option, Compiler FixesSchuyler Eldridge
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