Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.

1 files changed, 26 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 9b949274..971e8a1d 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -5,7 +5,7 @@ package transforms
 
 import firrtl.RenameMap
 import firrtl.annotations._
-import firrtl.transforms.DedupModules
+import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
 
 
 /**
@@ -553,5 +553,30 @@ class DedupModuleTests extends HighTransformSpec {
       """.stripMargin
     execute(input, check, Seq.empty)
   }
+  "modules" should "not be deduped if the NoCircuitDedupAnnotation (or --no-dedup option) is supplied" in {
+    val input =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    val check =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    execute(input, check, Seq(NoCircuitDedupAnnotation))
+  }
 }