Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.

3 files changed, 45 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index 47083cb4..189701dc 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -7,6 +7,7 @@ import firrtl.Parser._
 import firrtl.ir.Circuit
 import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation}
 import firrtl.passes.clocklist.ClockListAnnotation
+import firrtl.transforms.NoCircuitDedupAnnotation
 import logger.LogLevel
 import scopt.OptionParser
 
@@ -476,6 +477,15 @@ trait HasFirrtlOptions {
       "Do NOT run dead code elimination"
     }
 
+  parser.opt[Unit]("no-dedup")
+    .foreach { _ =>
+      firrtlOptions = firrtlOptions.copy(
+        annotations = firrtlOptions.annotations :+ NoCircuitDedupAnnotation
+      )
+    }.text {
+    "Do NOT dedup modules"
+  }
+
   parser.note("")
 }
 
diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala
index 83daad7f..609b5935 100644
--- a/src/main/scala/firrtl/transforms/Dedup.scala
+++ b/src/main/scala/firrtl/transforms/Dedup.scala
@@ -20,6 +20,8 @@ case class NoDedupAnnotation(target: ModuleName) extends SingleTargetAnnotation[
   def duplicate(n: ModuleName): NoDedupAnnotation = NoDedupAnnotation(n)
 }
 
+case object NoCircuitDedupAnnotation extends NoTargetAnnotation
+
 /** Only use on legal Firrtl.
   *
   * Specifically, the restriction of instance loops must have been checked, or else this pass can
@@ -34,9 +36,13 @@ class DedupModules extends Transform {
     * @return A transformed Firrtl AST
     */
   def execute(state: CircuitState): CircuitState = {
-    val noDedups = state.annotations.collect { case NoDedupAnnotation(ModuleName(m, c)) => m }
-    val (newC, renameMap) = run(state.circuit, noDedups, state.annotations)
-    state.copy(circuit = newC, renames = Some(renameMap))
+    if (state.annotations.contains(NoCircuitDedupAnnotation)) {
+      state
+    } else {
+      val noDedups = state.annotations.collect { case NoDedupAnnotation(ModuleName(m, c)) => m }
+      val (newC, renameMap) = run(state.circuit, noDedups, state.annotations)
+      state.copy(circuit = newC, renames = Some(renameMap))
+    }
   }
 
   /** Deduplicates a circuit, and records renaming
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 9b949274..971e8a1d 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -5,7 +5,7 @@ package transforms
 
 import firrtl.RenameMap
 import firrtl.annotations._
-import firrtl.transforms.DedupModules
+import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
 
 
 /**
@@ -553,5 +553,30 @@ class DedupModuleTests extends HighTransformSpec {
       """.stripMargin
     execute(input, check, Seq.empty)
   }
+  "modules" should "not be deduped if the NoCircuitDedupAnnotation (or --no-dedup option) is supplied" in {
+    val input =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    val check =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    execute(input, check, Seq(NoCircuitDedupAnnotation))
+  }
 }