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AgeCommit message (Expand)Author
2020-03-25Update scalatest 3.1.0 (#1383)Jim Lawson
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
2020-03-16Check for module name conflictsAlbert Magyar
2020-03-13Make InlineInstances invalidate ResolveKindsJack Koenig
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
2020-03-12Add out-of-bounds literal access test for ReplaceAccessesAlbert Magyar
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
2020-03-07Add firrtl-json serializers (#1430)Adam Izraelevitz
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
2020-03-02Remove new unreachables in EliminateTargetPathsSchuyler Eldridge
2020-02-19Add optionalPrerequisites to Dependency APISchuyler Eldridge
2020-02-19Add dependency prettyPrint, visualization updatesSchuyler Eldridge
2020-02-19Add additional PhaseManager testsSchuyler Eldridge
2020-02-19Support Singleton Dependencies (#1275)Albert Magyar
2020-02-18Add test case for reachableFrom behavior w.r.t. including rootAlbert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
2020-02-11Add InstanceGraph.staticInstanceCount testsSchuyler Eldridge
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
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