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AgeCommit message (Expand)Author
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add test for ConvertAssertsAlbert Magyar
2020-06-25Test both LowerCaseNames and UpperCaseNamesSchuyler Eldridge
2020-06-25Add a second instance to Verilog keyword testSchuyler Eldridge
2020-06-25Test ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
2020-06-25Test ManipulateNamesSpecSchuyler Eldridge
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-06-23Add support for ValidIf to ProtoBuf [de]serializationJack Koenig
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-06-22Support Memory Initialization for Simulation and FPGA Flows (#1645)Kevin Laeufer
2020-06-22recore of Attributes (#1643)Jiuyang Liu
2020-06-19RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)Albert Chen
2020-06-10Build ArrayBuffers in Block.mapStmt (#1669)Jack Koenig
2020-06-04Add test case for retype-based component renaming in DedupModulesAlbert Magyar
2020-06-04Add unit test for Utils.expandRefAlbert Magyar
2020-06-03Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}C...Schuyler Eldridge
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Fix equivalence tests (#853)Albert Chen
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
2020-05-13Add test of {Lower, Upper}CaseNamesSchuyler Eldridge
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
2020-05-11Have AppendInfo use MultiInfo, rather than appending with : (#1580)Adam Izraelevitz
2020-05-11Add andr, orr, xorr literal const prop testsSchuyler Eldridge
2020-05-08deprecating BackendCompilationUtilities trait for object (#1575)Deborah Soung
2020-05-06Update scalatest to 3.1.1 (#1405)Scala Steward
2020-05-05before/after initial block macros (#1550)Deborah Soung
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-04-20Add test cases for illegal casts to AsyncReset / ClockAlbert Magyar
2020-04-20Remove repetitive pass lists from WidthTestsAlbert Magyar
2020-04-20Avoid casting 2-bit interval to AsyncReset in testAlbert Magyar
2020-04-14Add Paul's async-reset self-init case as a testAlbert Magyar
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
2020-04-13Add test-case for explicit padding of SInts in mverilog compilerAlbert Magyar
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Add test of mixing -e with -E in FirrtlMainSpecSchuyler Eldridge
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
2020-04-10Add ground type serializer (#1502)Albert Chen
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
2020-03-30Add previously failing pad(cast(lit)) example as a test caseAlbert Magyar
2020-03-26Support octal and binary literal formats as described in the specAlbert Magyar
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