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AgeCommit message (Expand)Author
2020-08-05Deprecate InstanceGraph (#1800)Kevin Laeufer
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
2020-07-31Avoid repeated inlining in FlattenRegUpdate (#1727)Jack Koenig
2020-07-31[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)Jiuyang Liu
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
2020-07-29[2.13] toSeq, Unit -> (), and postfix fixesKevin Laeufer
2020-07-29[2.13] Range.Double -> Range.BigDecimalKevin Laeufer
2020-07-29WiringTransform: fix non-determinism (#1799)Kevin Laeufer
2020-07-29RemoveWires: improve dependencies and declare ResolveKinds as an invalidation...Kevin Laeufer
2020-07-29InferTypes: fix bugs with unknown widths on ports and memories (#1769)Kevin Laeufer
2020-07-29RenameMapSpec: try rename instance and port (#1776)Kevin Laeufer
2020-07-27Add Conditionally scoping tests to CheckSpecAlbert Magyar
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
2020-07-23fix reduction op bug ConstantPropagation (#1746)Albert Chen
2020-07-23mask bits when propagating bitwise ops (#1745)Albert Chen
2020-07-23Update negative literal emission (#1782)Albert Chen
2020-07-18Faster dedup instance graph (#1732)Kevin Laeufer
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
2020-07-16Simplify CustomTransformSpecSchuyler Eldridge
2020-07-16Remove overlapping inputForm=LowForm testsSchuyler Eldridge
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
2020-07-14Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-14Fix parsing of info on multi-line registers (#1735)Jack Koenig
2020-07-08dedup: use structural sha256 hash instead of agnostify and serialize (#1731)Kevin Laeufer
2020-07-08ir: add faster serializer (#1694)Kevin Laeufer
2020-07-07verification: emit mesage as Verilog comment (#1712)Kevin Laeufer
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add test for ConvertAssertsAlbert Magyar
2020-06-25Test both LowerCaseNames and UpperCaseNamesSchuyler Eldridge
2020-06-25Add a second instance to Verilog keyword testSchuyler Eldridge
2020-06-25Test ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
2020-06-25Test ManipulateNamesSpecSchuyler Eldridge
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-06-23Add support for ValidIf to ProtoBuf [de]serializationJack Koenig
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-06-22Support Memory Initialization for Simulation and FPGA Flows (#1645)Kevin Laeufer
2020-06-22recore of Attributes (#1643)Jiuyang Liu
2020-06-19RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)Albert Chen
2020-06-10Build ArrayBuffers in Block.mapStmt (#1669)Jack Koenig
2020-06-04Add test case for retype-based component renaming in DedupModulesAlbert Magyar
2020-06-04Add unit test for Utils.expandRefAlbert Magyar
2020-06-03Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}C...Schuyler Eldridge
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
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