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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Don't create nodes to hold Muxes with >0 void cases
* Added test case demonstrating void error
* Memoize intermediate expression when checking for WVoid-ness
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* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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