Add Tests for Check Initialization

1 files changed, 82 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
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+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
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+/*
+Copyright (c) 2014 - 2016 The Regents of the University of
+California (Regents). All Rights Reserved.  Redistribution and use in
+source and binary forms, with or without modification, are permitted
+provided that the following conditions are met:
+   * Redistributions of source code must retain the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer.
+   * Redistributions in binary form must reproduce the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer in the documentation and/or other materials
+     provided with the distribution.
+   * Neither the name of the Regents nor the names of its contributors
+     may be used to endorse or promote products derived from this
+     software without specific prior written permission.
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
+ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
+ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
+TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+MODIFICATIONS.
+*/
+
+package firrtlTests
+
+import java.io._
+import org.scalatest._
+import org.scalatest.prop._
+import firrtl._
+import firrtl.passes._
+
+class CheckInitializationSpec extends FirrtlFlatSpec {
+  private def parse(input: String) = Parser.parse("", input.split("\n").toIterator, false)
+  private val passes = Seq(
+     ToWorkingIR,
+     CheckHighForm,
+     ResolveKinds,
+     InferTypes,
+     CheckTypes,
+     ResolveGenders,
+     CheckGenders,
+     InferWidths,
+     CheckWidths,
+     PullMuxes,
+     ExpandConnects,
+     RemoveAccesses,
+     ExpandWhens,
+     CheckInitialization)
+  "Missing assignment in consequence branch" should "trigger a PassException" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input p : UInt<1>
+        |    wire x : UInt<32>
+        |    when p :
+        |      x <= UInt(1)""".stripMargin
+    intercept[PassExceptions] {
+      passes.foldLeft(parse(input)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+  "Missing assignment in alternative branch" should "trigger a PassException" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input p : UInt<1>
+        |    wire x : UInt<32>
+        |    when p :
+        |    else :
+        |      x <= UInt(1)""".stripMargin
+    intercept[PassExceptions] {
+      passes.foldLeft(parse(input)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+}