sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2017-04-18	"Scope" test resource (top.cpp). (#398)	Jim Lawson
2017-01-29	Keep firrtl's simulation environment in sync with chisel's. (#425)	Jim Lawson
2016-12-08	Clk2clock - rename the implicit "clk" module input "clock" (#387)	Jim Lawson
2016-11-23	Stringified annotations (#367)	Adam Izraelevitz
2016-11-05	Fix CHIRRTL bugs (#355)	Donggyu
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-11-04	Refactor Compilers and Transforms	jackkoenig
2016-10-26	Add RawString ExtModule parameter support	jackkoenig
2016-10-26	Add Support for Parameterized ExtModules and Name Override	jackkoenig
2016-10-26	Add ExtModule Tests	jackkoenig
2016-10-07	Add test for Firrtl mems with no ports (#327)	Jack Koenig
2016-09-12	Add LegalizeSpec for testing Verilog Legalization pass	Jack
2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz
2016-05-03	Add Expand Whens test	jackkoenig
2016-05-03	Make simulations that time out fail when run in firrtlTests	jackkoenig
2016-04-20	Add tests for CHIRRTL mem port definitions.	jackkoenig
2016-04-20	Fix top.cpp reset race condition #137	jackkoenig
2016-04-08	Add small test for issue #105	jackkoenig
2016-03-15	Revamp string literal handling	jackkoenig
2016-03-03	Add some integration tests: successful compilation and execution	jackkoenig
2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and comp...	Jack