Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

12 files changed, 73 insertions, 73 deletions

diff --git a/src/test/resources/blackboxes/MultiExtModuleTester.fir b/src/test/resources/blackboxes/MultiExtModuleTester.fir
index fa8effdf..82ac172f 100644
--- a/src/test/resources/blackboxes/MultiExtModuleTester.fir
+++ b/src/test/resources/blackboxes/MultiExtModuleTester.fir
@@ -9,7 +9,7 @@ circuit MultiExtModuleTester :
     output bar : UInt<16>
 
   module MultiExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut1 of SimpleExtModule
@@ -22,16 +22,16 @@ circuit MultiExtModuleTester :
 
     when not(reset) :
       when neq(dut1.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
         when neq(dut2.bar, UInt(5678)) :
-          printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-          stop(clk, not(reset), 1)
+          printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+          stop(clock, not(reset), 1)
         else :
           when neq(dut3.bar, UInt(101)) :
-            printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-            stop(clk, not(reset), 1)
+            printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+            stop(clock, not(reset), 1)
           else :
-            stop(clk, not(reset), 0)
+            stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
index eb9ba13f..3167cded 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
@@ -21,7 +21,7 @@ circuit ParameterizedExtModuleTester :
     parameter TYP = 'bit [1:0]'
 
   module ParameterizedExtModuleTester  :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut1 of ParameterizedExtModule_1
@@ -32,12 +32,12 @@ circuit ParameterizedExtModuleTester :
 
     when not(reset) :
       when neq(dut1.bar, UInt(1003)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
         when neq(dut2.bar, UInt(1008)) :
-          printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-          stop(clk, not(reset), 1)
+          printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+          stop(clock, not(reset), 1)
         else :
-          stop(clk, not(reset), 0)
+          stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/RenamedExtModuleTester.fir b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
index 9e807813..37338c9f 100644
--- a/src/test/resources/blackboxes/RenamedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
@@ -7,7 +7,7 @@ circuit RenamedExtModuleTester :
     defname = SimpleExtModule
 
   module RenamedExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of ThisIsJustTheFirrtlName
@@ -16,8 +16,8 @@ circuit RenamedExtModuleTester :
 
     when not(reset) :
       when neq(dut.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
-        stop(clk, not(reset), 0)
+        stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/SimpleExtModuleTester.fir b/src/test/resources/blackboxes/SimpleExtModuleTester.fir
index 264ce5fa..7118ec9f 100644
--- a/src/test/resources/blackboxes/SimpleExtModuleTester.fir
+++ b/src/test/resources/blackboxes/SimpleExtModuleTester.fir
@@ -5,7 +5,7 @@ circuit SimpleExtModuleTester :
     output bar : UInt<16>
 
   module SimpleExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of SimpleExtModule
@@ -14,8 +14,8 @@ circuit SimpleExtModuleTester :
 
     when not(reset) :
       when neq(dut.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
-        stop(clk, not(reset), 0)
+        stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/features/ChirrtlMems.fir b/src/test/resources/features/ChirrtlMems.fir
index 6cc9f122..c51e3b78 100644
--- a/src/test/resources/features/ChirrtlMems.fir
+++ b/src/test/resources/features/ChirrtlMems.fir
@@ -1,22 +1,22 @@
 ; See LICENSE for license details.
 circuit ChirrtlMems :
   module ChirrtlMems :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     cmem ram : UInt<32>[16]
-    node newClock = clk
+    node newClock = clock
 
     wire wen : UInt<1>
     wen <= not(reset) ; Don't const prop me!
 
-    reg raddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+    reg raddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
     raddr <= add(raddr, UInt(1))
     infer mport r = ram[raddr], newClock
 
     when wen :
-      node newerClock = clk
-      reg waddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+      node newerClock = clock
+      reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
       waddr <= add(waddr, UInt(1))
       infer mport w = ram[waddr], newerClock
       w <= waddr
@@ -27,8 +27,8 @@ circuit ChirrtlMems :
     when not(reset) :
       when gt(waddr, UInt(1)) :
         when neq(r, raddr) :
-          printf(clk, UInt(1), "Assertion failed! r =/= raddr\n")
-          stop(clk, UInt(1), 1) ; Failure!
+          printf(clock, UInt(1), "Assertion failed! r =/= raddr\n")
+          stop(clock, UInt(1), 1) ; Failure!
       when eq(raddr, UInt(15)) :
-        stop(clk, UInt(1), 0) ; Success!
+        stop(clock, UInt(1), 0) ; Success!
     
diff --git a/src/test/resources/features/CustomTransform.fir b/src/test/resources/features/CustomTransform.fir
index 61bd6ad2..de00f261 100644
--- a/src/test/resources/features/CustomTransform.fir
+++ b/src/test/resources/features/CustomTransform.fir
@@ -2,21 +2,21 @@
 circuit CustomTransform :
   ; Replaced in custom transform by an implementation
   extmodule Delay :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     input a : UInt<32>
     input en : UInt<1>
     output b : UInt<32>
 
   module CustomTransform :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg cycle : UInt<32>, clk with : (reset => (reset, UInt<32>(0)))
+    reg cycle : UInt<32>, clock with : (reset => (reset, UInt<32>(0)))
     cycle <= tail(add(cycle, UInt<32>(1)), 1)
 
     inst delay of Delay
-    delay.clk <= clk
+    delay.clock <= clock
     delay.reset <= reset
     delay.a <= UInt(0)
     delay.en <= UInt(0)
@@ -26,9 +26,9 @@ circuit CustomTransform :
       delay.a <= UInt("hdeadbeef")
     when eq(cycle, UInt(1)) :
       when neq(delay.b, UInt("hdeadbeef")) :
-        printf(clk, UInt(1), "Assertion failed!\n")
-        stop(clk, UInt(1), 1)
+        printf(clock, UInt(1), "Assertion failed!\n")
+        stop(clock, UInt(1), 1)
     when eq(cycle, UInt(2)) :
-      printf(clk, UInt(1), "Success!\n")
-      stop(clk, UInt(1), 0)
+      printf(clock, UInt(1), "Success!\n")
+      stop(clock, UInt(1), 0)
 
diff --git a/src/test/resources/features/NestedSubAccessTester.fir b/src/test/resources/features/NestedSubAccessTester.fir
index c40da6a0..84b4cfbe 100644
--- a/src/test/resources/features/NestedSubAccessTester.fir
+++ b/src/test/resources/features/NestedSubAccessTester.fir
@@ -12,7 +12,7 @@ circuit NestedSubAccessTester :
     out <= vec[foo[index]]
 
   module NestedSubAccessTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of NestedSubAccess
@@ -22,9 +22,9 @@ circuit NestedSubAccessTester :
     dut.foo[2] <= UInt(1)
 
     when neq(dut.out, UInt(4)) :
-      printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-      stop(clk, not(reset), 1)
+      printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+      stop(clock, not(reset), 1)
     else :
-      stop(clk, not(reset), 0)
+      stop(clock, not(reset), 0)
 
 
diff --git a/src/test/resources/features/Printf.fir b/src/test/resources/features/Printf.fir
index a19e2493..5e065b9c 100644
--- a/src/test/resources/features/Printf.fir
+++ b/src/test/resources/features/Printf.fir
@@ -1,17 +1,17 @@
 ; See LICENSE for license details.
 circuit Printf : 
   module Printf : 
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg count : UInt<10>, clk with :
+    reg count : UInt<10>, clock with :
       reset => (reset, UInt<6>(0))
-    reg const : UInt<32> clk with :
+    reg const : UInt<32> clock with :
       reset => (reset, UInt(123456))
 
     node notReset = not(reset)
     count <= add(count, UInt(1))
-    printf(clk, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
+    printf(clock, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
 
     when eq(count, UInt(255)) :
-      stop(clk, UInt(1), 0)
+      stop(clock, UInt(1), 0)
diff --git a/src/test/resources/features/ZeroPortMem.fir b/src/test/resources/features/ZeroPortMem.fir
index 7e509ecf..96327f5c 100644
--- a/src/test/resources/features/ZeroPortMem.fir
+++ b/src/test/resources/features/ZeroPortMem.fir
@@ -1,7 +1,7 @@
 ; See LICENSE for license details.
 circuit ZeroPortMem :
   module ZeroPortMem :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     mem mymem :
@@ -16,8 +16,8 @@ circuit ZeroPortMem :
 
     when not(reset) :
       when eq(foo, UInt<32>("hdeadbeef")) :
-        stop(clk, UInt(1), 0) ; Success !
+        stop(clock, UInt(1), 0) ; Success !
       else :
-        printf(clk, UInt(1), "Assertion failed!\n")
-        stop(clk, UInt(1), 1) ; Failure!
+        printf(clock, UInt(1), "Assertion failed!\n")
+        stop(clock, UInt(1), 1) ; Failure!
 
diff --git a/src/test/resources/passes/ExpandWhens/ExpandWhens.fir b/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
index 7d4c4cbb..291cf1b4 100644
--- a/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
+++ b/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
@@ -1,12 +1,12 @@
 ; See LICENSE for license details.
 circuit ExpandWhens :
   module ExpandWhens :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     node done = UInt(6)
 
-    reg x : UInt<16>, clk with :
+    reg x : UInt<16>, clock with :
       reset => (reset, UInt(0))
     x <= x
 
@@ -30,18 +30,18 @@ circuit ExpandWhens :
         when lt(x, UInt(5)) :
           x <= UInt(5)
 
-    reg count : UInt<16>, clk with :
+    reg count : UInt<16>, clock with :
       reset => (reset, UInt(0))
     when neq(count, done) :
       count <= add(count, UInt(1))
 
-    printf(clk, UInt(1), "count = %d, x = %d\n", count, x)
+    printf(clock, UInt(1), "count = %d, x = %d\n", count, x)
 
     when not(reset) :
       when neq(x, count) : 
-        printf(clk, UInt(1), "Assertion failed! x =/= count!\n")
-        stop(clk, UInt(1), 1)
+        printf(clock, UInt(1), "Assertion failed! x =/= count!\n")
+        stop(clock, UInt(1), 1)
       when eq(x, done) :
-        stop(clk, UInt(1), 0)
+        stop(clock, UInt(1), 0)
 
      
diff --git a/src/test/resources/passes/Legalize/Legalize.fir b/src/test/resources/passes/Legalize/Legalize.fir
index 8d8ac8bd..716dff83 100644
--- a/src/test/resources/passes/Legalize/Legalize.fir
+++ b/src/test/resources/passes/Legalize/Legalize.fir
@@ -1,18 +1,18 @@
 ; See LICENSE for license details.
 circuit Legalize :
   module Legalize :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     ; Count till done
     node done = UInt(6)
-    reg count : UInt<16>, clk with :
+    reg count : UInt<16>, clock with :
       reset => (reset, UInt(0))
     when neq(count, done) :
       count <= add(count, UInt(1))
     when not(reset) :
       when eq(count, done) :
-        stop(clk, UInt(1), 0)
+        stop(clock, UInt(1), 0)
 
     ; Begin Test
     ; Check assignment to smaller width
@@ -20,22 +20,22 @@ circuit Legalize :
     wire y : UInt<16>
     y <- x
     when neq(y, UInt("hbeef")) :
-      printf(clk, UInt(1), "Assertion failed!\n y != beef\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n y != beef\n")
+      stop(clock, UInt(1), 1)
 
     ; Check bit select of literal
     node b = bits(UInt("hd0"), 7, 5)
     node b2 = bits(UInt("h9"), 3, 3)
     when neq(b, UInt(6)) :
-      printf(clk, UInt(1), "Assertion failed!\n b != 6\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n b != 6\n")
+      stop(clock, UInt(1), 1)
     when neq(b2, UInt(1)) :
-      printf(clk, UInt(1), "Assertion failed!\n b2 != 1\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n b2 != 1\n")
+      stop(clock, UInt(1), 1)
 
     ; Check padding of literal
     node bar = pad(SInt(-1), 16)
     node bar_15 = bits(bar, 15, 15)
     when neq(bar_15, UInt(1)) :
-      printf(clk, UInt(1), "Assertion failed!\n bar_15 != 0\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n bar_15 != 0\n")
+      stop(clock, UInt(1), 1)
diff --git a/src/test/resources/top.cpp b/src/test/resources/top.cpp
index c117126d..08ad42fa 100644
--- a/src/test/resources/top.cpp
+++ b/src/test/resources/top.cpp
@@ -46,10 +46,10 @@ int main(int argc, char** argv) {
       top->reset = 0;   // Deassert reset
     }
     if ((main_time % 10) == 1) {
-      top->clk = 1;       // Toggle clock
+      top->clock = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clk = 0;
+      top->clock = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE
@@ -70,10 +70,10 @@ int main(int argc, char** argv) {
   vluint64_t end_time = main_time + 100;
   while (main_time < end_time) {
     if ((main_time % 10) == 1) {
-      top->clk = 1;       // Toggle clock
+      top->clock = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clk = 0;
+      top->clock = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE