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The fix for PR #305 caused a new compile warning from Cadence Incisive:
always @(*) begin end
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ncelab: *W,STARMT (../TestHarness.MyConfig.v,196147|9): This @* expands to empty list, will never wake up.
This change satisfies all of: VCS, Incisive, Questa, Vivado, Verilator.
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This allows the replseqmem transform to not deduplicate
some memories, based on their name.
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Also add support for width inference
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This comment causes vcs to treat this as a spare memory,
so it will dynamically allocate the required memory, and can
support very large reg constructs this way. This is useful for
test bench memories that might be simulating back DRAM or the like.
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* Rework Attach to work on arbitrary Analog hierarchies
If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.
* Add helper functions for creating WRef from Reg and Wire
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This fixes an issue I was having with my ClockListAnnotations being duplicated.
h/t @azidar
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Fixes ucb-bar/chisel3#420
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* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests
* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
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Will place tests in ./test_run_dir/ instead of /tmp/
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* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory
* A little bit of style cleanup
* A little bit of style cleanup
* Fix the driver, wasn't appending targetDir properly
Add some docs
* test had wrong value now that targetdir is added to annnos
* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line
* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there
* targetDir annotation is targeted to a CircuitName("All")
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* type conversions between sint/fixed and uint added at memory interfaces for replseqmem
* turns out asFixed requires bp as constant in PrimOps (really should be documented)
* fixed legalizeconnects to handle FixedPt
* added tests for replseqmem failure with signed types
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* Move BackendCompilationUtilities into a util package for use by chisel3.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
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Add a test for cmem and smem with fixed point numbers
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* Add pass that fixes up widths with modulus operator for verilog
* Add basic test for Verilog emission of Rem
* Oops, left in some printlns.
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Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320
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* Fixes for Annotation serialized/deserialize
Made serializer agree with deserializer on text representation
Re-ordered serializations of Named subclasses to be C or C.m or C.m.c where C=circuit, m=module, c=component
Note: component may contain dots
Added serialize deserialize tests to AnnotationSpec
Did some style cleanup on AnnotationSpec
Added explicit return tupe on SimpleTransformSpec#execute
* Make explicit Util.error
remove commented code
* Make Annotation#serialize a nicer format
fix import there and remove new on case class
* In firrtl Driver.execute use annotations passed in through optionsManager#firrtlOptions if nonEmpty
otherwise read the annotations in from an annotations file
Add new option to override this behavior, --force-append-anno-file will append annotations in file
to any that are passed in
A few other style fixes to Driver: remove new with case classes. don't use match when if(boolean) will do
* Added tests of malformed component and circuit names
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Also run CheckTypes after ExpandWhens
Fixes #330
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FileInfo is merged
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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* Rewrote inline xform to fix quadratic perf. bug
Turns out caching previously inlined modules is not useful
The previous algorithm in a module, would flatten an instance's children, then
flatten that instance. This caused all instances to be effectively
inlined the number of times of its depth in the instance hierarchy,
making it O(n*d*s), where n is the number of instances, and d is the depth
of the instance, and s is the number of statements in the instance.
The new algorithm directly inlines a module by keeping track of the
parents of that instance, making it constant time with the number of
instantiated instances.
* Minor style fixes
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* Fixed multi wiring
* Minor style changes
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* Fix wrong omitting same clocked nondirect children
* Minor style fixes
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Required for passing all chisel3 tests
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Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error
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This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.
An example is:
reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
node x = add(r, r)
r <= x
Here, r's width follows the following formula, which cannot be solved:
rWidth >= max(max(rWidth, rWidth) + 1, 2)
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Added clocklist transform
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getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
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Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals
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* handle uninferred ports gracefully in RemoveCHIRRTL
memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL
* fix CInferTypes
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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