diff options
| author | Colin Schmidt | 2017-02-13 15:09:28 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-02-13 15:09:28 -0800 |
| commit | 8f3c7d357fd6c97121d5adbb0ca09ce34f763374 (patch) | |
| tree | c7bcc5ae58166421c4cc8806376ea7c4516243cf /src/main | |
| parent | 7b2a3bc74d5fd0303c0056b4cb785fb34d7806bc (diff) | |
Emit memories larger than 512 MB with a sparse annotation (#438)
This comment causes vcs to treat this as a spare memory,
so it will dynamically allocate the required memory, and can
support very large reg constructs this way. This is useful for
test bench memories that might be simulating back DRAM or the like.
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 36e4929a..eb219b6d 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -454,7 +454,9 @@ class VerilogEmitter extends Emitter with PassBased { instdeclares += Seq(");") sx case sx: DefMemory => - declare("reg", sx.name, VectorType(sx.dataType, sx.depth)) + val fullSize = sx.depth * (sx.dataType match { case GroundType(IntWidth(width)) => width }) + val decl = if (fullSize > (1 << 29)) "reg /* sparse */" else "reg" + declare(decl, sx.name, VectorType(sx.dataType, sx.depth)) initialize_mem(sx) if (sx.readLatency != 0 || sx.writeLatency != 1) throw EmitterException("All memories should be transformed into " + |