diff options
| author | Donggyu | 2016-11-05 21:23:14 -0700 |
|---|---|---|
| committer | GitHub | 2016-11-05 21:23:14 -0700 |
| commit | e05ca2b2edb3b1d3fc191864ff31e2b5fc079b42 (patch) | |
| tree | 39d1c02f347116f3f4fa45610030e6f0d078c233 /src/main | |
| parent | 82da5e7903817b877bff3c07e09b0b7e9d009351 (diff) | |
Fix CHIRRTL bugs (#355)
* handle uninferred ports gracefully in RemoveCHIRRTL
memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL
* fix CInferTypes
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/InferTypes.scala | 7 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala index 372d2942..0e503115 100644 --- a/src/main/scala/firrtl/passes/InferTypes.scala +++ b/src/main/scala/firrtl/passes/InferTypes.scala @@ -90,7 +90,7 @@ object CInferTypes extends Pass { case (e: SubIndex) => e copy (tpe = sub_type(e.expr.tpe)) case (e: SubAccess) => e copy (tpe = sub_type(e.expr.tpe)) case (e: DoPrim) => PrimOps.set_primop_type(e) - case (e: Mux) => e copy (tpe = mux_type(e.tval,e.tval)) + case (e: Mux) => e copy (tpe = mux_type(e.tval, e.fval)) case (e: ValidIf) => e copy (tpe = e.value.tpe) case e @ (_: UIntLiteral | _: SIntLiteral) => e } @@ -103,8 +103,9 @@ object CInferTypes extends Pass { types(sx.name) = sx.tpe sx case sx: DefNode => - types(sx.name) = sx.value.tpe - sx + val sxx = (sx map infer_types_e(types)).asInstanceOf[DefNode] + types(sxx.name) = sxx.value.tpe + sxx case sx: DefMemory => types(sx.name) = MemPortUtils.memType(sx) sx diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index abd45f75..aae4ca80 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -52,6 +52,7 @@ object RemoveCHIRRTL extends Pass { case MRead => p.readers += MPort(sx.name, sx.exps(1)) case MWrite => p.writers += MPort(sx.name, sx.exps(1)) case MReadWrite => p.readwriters += MPort(sx.name, sx.exps(1)) + case MInfer => // direction may not be inferred if it's not being used } mports(sx.mem) = p case _ => @@ -119,6 +120,7 @@ object RemoveCHIRRTL extends Pass { raddrs(e.name) = SubField(SubField(Reference(sx.mem, ut), sx.name, ut), "en", ut) case _ => ens += "en" } + case MInfer => // do nothing if it's not being used } Block( (addrs map (x => Connect(sx.info, SubField(SubField(Reference(sx.mem, ut), sx.name, ut), x, ut), sx.exps.head))) ++ |