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AgeCommit message (Expand)Author
2015-05-04Added a few more error checks. Not tested yet. Fixed bug in pad type inferenceazidar
2015-05-04mergejackbackrack
2015-05-04Fixed change where type of mux-ss was incorrectazidar
2015-05-02mergejackbackrack
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...azidar
2015-05-01add arsh refsjackbackrack
2015-05-01Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one)azidar
2015-05-01Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp...azidar
2015-05-01mergejackbackrack
2015-05-01adjust sizeof to be correctjackbackrack
2015-05-01Fixed bug where the enable was looked at for lowering MUX.azidar
2015-04-30mergejackbackrack
2015-04-30Fixed assignment to outputs not getting emitted from Expand When passazidar
2015-04-30mergejackbackrack
2015-04-30turn off printingjackbackrack
2015-04-30Fixed bug that added multiple arguements to OR, instead of a reduce-orazidar
2015-04-29mergejackbackrack
2015-04-29mergejackbackrack
2015-04-29add dyn shifts to flo backendjackbackrack
2015-04-29Fixed bug where a node's width was not equal to its value'sazidar
2015-04-29Made temp name generation counter, as well as the name, based off the eventua...azidar
2015-04-29Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correctazidar
2015-04-29mergejackbackrack
2015-04-29turn off printingjackbackrack
2015-04-29Added dshl and dshrazidar
2015-04-28mergejackbackrack
2015-04-28Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....azidar
2015-04-27mergejackbackrack
2015-04-27fix ops to get tests passing through flo-llvmjackbackrack
2015-04-27Removed WRegInitazidar
2015-04-27Added on-resetazidar
2015-04-26mergejackbackrack
2015-04-26pad uses rsh with zero shiftjackbackrack
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
2015-04-24Fixed switch statementazidar
2015-04-24NEG now propogates input args plus oneazidar
2015-04-24Partial commitazidar
2015-04-24mergejackbackrack
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
2015-04-24Updated TODO. Added backwards with prop for as and bitsazidar
2015-04-24mergejackbackrack
2015-04-24Incorrectly propagated width constraint for non-muxes. This is only true for ...azidar
2015-04-24mergejackbackrack
2015-04-24flo backend consts get widths and read enable goes to onejackbackrack
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-04-24Fixed width inference bug where later constraints on the output width were no...azidar
2015-04-24Inflightazidar
2015-04-24Merge pull request #5 from jackbackrack/masterAdam Izraelevitz
2015-04-24mergejackbackrack
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