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| author | azidar | 2015-04-24 14:58:38 -0700 |
|---|---|---|
| committer | azidar | 2015-04-24 14:58:38 -0700 |
| commit | 2006198a53328e3898bcbe69429b751c065ea802 (patch) | |
| tree | 1e840fff48dc7f2f9588130e65043e3f9ae49204 /src/main | |
| parent | e6a55328fbae892311dd6359d8faed8f10f8aae4 (diff) | |
Incorrectly propagated width constraint for non-muxes. This is only true for muxes
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/stanza/primop.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index a1e9633f..a6b42e7c 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -279,7 +279,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : val w-var = VarWidth(gensym(`w)) val w* = if not contains?(all-args-not-equal,op(e)) : - val max-args-w = all-equal(List(w-var,map(width!,args(e)))) + val max-args-w = all-equal(map(width!,args(e))) switch {op(e) == _} : ADD-UU-OP : PlusWidth(max-args-w,IntWidth(1)) ADD-US-OP : PlusWidth(max-args-w,IntWidth(1)) |