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path: root/src/main/stanza/passes.stanza
AgeCommit message (Expand)Author
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect indexed...azidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-07-14Fixed bug in lowering, where the indexes to many-connects and accessors weren...azidar
2015-07-06Updated todoazidar
2015-07-01Updated TODO.azidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-02Added low firrtl check. Corrected bug in prefix matching in high firrtl checkazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops strict...azidar
2015-05-19Merge pull request #8 from jackbackrack/masterAdam Izraelevitz
2015-05-19get flo backend running again with no pads and generic operatorsjackbackrack
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18get coercion running for flo backend and disable negative lit checkjackbackrack
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-14mergejackbackrack
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-07do signed padding as welljackbackrack
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check t...azidar
2015-05-04mergejackbackrack
2015-05-04Fixed bug where instance types were not loweredazidar
2015-05-04add reduction operatorsjackbackrack
2015-05-04Merge pull request #6 from jackbackrack/masterAdam Izraelevitz
2015-05-02mergejackbackrack
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...azidar
2015-05-01add arsh refsjackbackrack