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AgeCommit message (Expand)Author
2021-06-03Replace mem macros renaming (#2243)Albert Chen
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
2021-05-21Optimize Annotation.getTargets (#2244)Jack Koenig
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
2021-05-21Annotation: override getTargets for SingleTargetAnnotation (#2241)Kevin Laeufer
2021-05-21WiringTransform: cannot run after RemoveWires (#2240)Kevin Laeufer
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
2021-05-17Use os-lib to rewrite Z3ModelChecker (#2223)Jiuyang Liu
2021-05-14Add JsonProtocol.serializeRecover (#2227)Jack Koenig
2021-05-13Implement MFC-style source locator compression (#2212)Jared Barocsi
2021-05-04Make MustDeduplicateAnnotation deletable (#2215)Jack Koenig
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
2021-04-19Hoist Transform timing to the Phase level (#2190)Jack Koenig
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
2021-04-13Add indent parameter to Serializer.serialize() (#2177)Jared Barocsi
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-03-04CSE SubAccesses (#2099)Jack Koenig
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-03-02Fix CI Checks (#2097)Jack Koenig
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