diff options
| author | Albert Magyar | 2021-03-09 23:15:29 -0800 |
|---|---|---|
| committer | Albert Magyar | 2021-04-05 12:00:02 -0700 |
| commit | 088c82244d58d7e5c8a6ad6e7e3bb1edaf81af3a (patch) | |
| tree | 7207d377f209e95e963bd23affa1f199a14697a5 /src | |
| parent | ca8b670eac0b0def66249738e52ef8137d30a8b5 (diff) | |
Specify that SimplifyMems invalidates InferTypes
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/SimplifyMems.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index 8ecc484a..81c40dd4 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -23,7 +23,10 @@ class SimplifyMems extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty override def optionalPrerequisiteOf = Forms.MidEmitters - override def invalidates(a: Transform) = false + override def invalidates(a: Transform) = a match { + case InferTypes => true + case _ => false + } def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = { val moduleNS = Namespace(m) |
