| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-24 | Fixed printf bugs in scala and stanza versions. Required special casing print... | Adam Izraelevitz |
| 2016-02-09 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-02-09 | Added chirrtl passes, need to update parser | azidar |
| 2016-02-09 | Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ... | azidar |
| 2016-02-09 | Moved check-high-form to operate on working ir | azidar |
| 2016-02-09 | Added remove accesses | azidar |
| 2016-02-09 | Added expand connect. Resolve now includes to working ir | azidar |
| 2016-02-09 | WIP. Got to-working-ir working | azidar |
| 2016-02-09 | WIP, nothing works. Starting creating working IR and necessary utils | azidar |
| 2016-02-08 | Escape quotes in strings before emitting as Verilog | Palmer Dabbelt |
| 2016-02-08 | Escape printf argument before emitting them | Palmer Dabbelt |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Fixed bug where you cannot extract from a single bit wire in verilog. #55. | azidar |
| 2016-01-28 | Fixed bug where needed to cast bit-operation inputs prior to verilog emission | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Add map of symbol->symbol for wdefinstance | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Fixed bug in lowering memories that had aggregate data types | azidar |
| 2016-01-16 | Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat... | azidar |
| 2016-01-16 | Reworked Verilog emission of registers to if/else instead of ?: | azidar |
| 2016-01-16 | No longer split on muxes | azidar |
| 2016-01-16 | Sped up remove access by checking a condition | azidar |
