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Fixes #2516
Previously,
reg r : UInt<8>, clock with :
reset => (p, UInt<8>(3))
r is invalid
would compile to:
reg r : UInt<8>, clock
r <= UInt<8>(0)
now it compiles to:
reg r : UInt<8>, clock
wire r_1 : UInt<8>
r_1 is invalid
r <= mux(reset, UInt<8>(3), r_1)
This is consistent with the behavior for a reset with an asynchronous
reset.
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Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.
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* Add FileInfo to asyncResetAlwaysBlocks
Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).
RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.
Async always blocks don't provide their only FileInfo, so there are no line numbers.
This commit gives async always block the extra FileInfo to show line numbers for them.
This code:
```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission
class Test extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val valid = RegInit(false.B)
valid := io.in
io.out := valid
}
object Test extends App {
new ChiselStage().execute(Array(), Seq(
ChiselGeneratorAnnotation(() => new Test()),
CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
))
}
```
will generate this Verilog:
```verilog
module Test(
input clock,
input reset,
input io_in,
output io_out
);
reg valid; // @[Playground.scala 10:22]
assign io_out = valid; // @[Playground.scala 12:10]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[Playground.scala 10:22]
valid <= 1'h0; // @[Playground.scala 10:22]
end else begin
valid <= io_in; // @[Playground.scala 11:9]
end
end
endmodule
```
they have correct line numbers (10, 10, 11).
* Add test for async always block line numbers
* Add comment for review
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* Fix unreachable code warning by changing match order
Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.
* Handle MemoryNoInit case in RtlilEmitter
* Remove use of deprecated logToFile
* Fix uses of LegalizeClocksTransform
Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.
* Remove use of CircuitForm in ZeroWidth
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* Add renamemap.MutableRenameMap which includes these methods without
deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
undeprecated a while ago
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Change AnnotationSeq underlying from List to Seq
It was nothing but pointless copying.
* Make propagateAnnotations faster
There was lots of expensive logic for very little benefit.
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1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix.
2. Add CustomRadixConfigFileAnnotation to output a JSON config file so
users can generate scripts on their own.
Reviewed-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: sinofp <sinofp@tuta.io>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Demonstrate a couple failing cases
* Have TopWiring ignore unnamed declarations as potential sources
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* Have Flatten & InlineInstances remove their annotations
* Format
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* Added RTLIL Backend.
* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.
* Fix build on scala 2.13
* Add additional equivalence test, make some bugfixes and perf opts to the emitter.
* Final changes as requested by Kevin, code cleanup, add support for formal cells.
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(#2324)
Both transforms are (most likely) not needed.
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The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* make PresetRegAnnotation public
this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
need to be initialized at the beginning of simulation
(e.g., for formal verification)
- to support preset registers in treadle
* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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Requested by reviewer.
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Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
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To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add --no-constant-propagation to disable constant propagation
* add test
* deprecate DisableFold.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Previously, InlineCasts could inline complex (ie. non-cast) Expressions
into other complex Expressions. Now it will only inline so long as there
no more than 1 complex Expression in the current nested Expression.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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The flow of a LHS SubAccess node may still be SourceFlow if the type of
the Vec element has a flip. Tweak the logic of CSESubAccesses to check
every Expression flow while recursing instead of just the flow of the
final SubAccess.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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With this PR the smt backend now supports memories
with more than two write ports and the conservative
memory modelling can be selectively turned off with
a new annotation.
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Fixes n^2 performance problem when dynamically indexing Vecs of
aggregate types.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* firrtl: add optional statement labels for stop, printf, assert, assume and cover
* test: parsing of statement labels
* ir: ensure that name is properly retained
* SymbolTable: add support for labled statements
* test: parsing statement labels
* test: lower types name collisions with named statements
* ignore empty names
* Inline: deal with named and unnamed statements
* RemoveWires: treat stop, printf and verification statements as "others"
* test: fix InlineInstance tests
* DeadCodeEliminations: statements are now als declarations
* CheckHighForm: ensure that statement names are not used as references
* CheckSpec: throw error if statement name collides
* add pass to automatically add missing statement names
* check: make sure that two statements cannot have the same name
* stmtLabel -> stmtName
* scalafmt
* add statement names to spec
* spec: meta data -> metadata
* EnsureStatementNames: explain naming algorithm
* remove returns
* better namespace use
* ir: add CanBeReferenced trait
* ir: add newline as jack requested
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This enables marking modules as "must deduplicate". If modules marked as
such do not deduplicate, the transform will create error reports and
make suggestions as to why deduplication failed.
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* Deprecate firrtl.passes.ToWorkingIR
Deprecate ToWorkingIR as it is now an identity transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Deprecate firrtl.stage.Forms.WorkingIR
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Switch from Forms.WorkingIR to Forms.MinimalHighForm
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This allows ConstantPropagation to be used in cases where
ValidIfs need to be maintained, e.g., in the formal backend.
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Check Unidoc on all versions of Scala
It is required for publishing and we publish every version
* Fix conflicting cross-version suffixes issue
When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version
for the fuzzer and benchmark projects even though they aren't really
relevant to the command. This may be a misconfiguration or a bug in
the unidoc plugin. Whatever the case, simply making it possible for
them to use the same version of Scala as the firrtl project (on which
they depend) fixes the issue.
* Match versions of Scala in build.sbt and CI
* Fix unidoc issues in 2.13.4
There is some bug in ScalaDoc not finding some links in firrtl.options
so those links were made absolute as a workaround.
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This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.
Add a test that a user can disable `a / a -> 1` with a
DisableFold(PrimOps.Div) annotation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add SortModules to transform to def-before-use
Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Add test of SortModules transform
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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It would replace them with a validif node with a UIntLiteral which can
lead to type errors.
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* split big Emitter to submodules.
* fix all deprecated warning.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
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Both use EliminateTargetPaths to duplicate modules based on annotations.
Currently, EliminateTargetPaths API is a little too limited so it
duplicates more than it should which effectively breaks Dedup whenever
DontTouchAnnotations are present.
Also, make ConstProp and DCE treat all HasDontTouches as local
annotations even if they are instance annotations. This is more
conservative but it is generally better to preserve deduplication than
to maximally optimize every instance.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* test multiinfo comparison and mux cond inlining
* loosen inlining conditions
* fix typo
* include dshlw
* fix test
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