diff options
| author | Nicolas Machado | 2021-09-28 20:18:48 -0700 |
|---|---|---|
| committer | GitHub | 2021-09-29 03:18:48 +0000 |
| commit | e70ee5367c864e55ff16637430b712666b7dbd2b (patch) | |
| tree | a448d6cb6f232f31ef05573f7c5fd43f950060a9 /src/main/scala/firrtl/transforms | |
| parent | a921e1230b389be87d993f3016cb46174b1ebfad (diff) | |
Add RTLIL Backend. (#2331)
* Added RTLIL Backend.
* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.
* Fix build on scala 2.13
* Add additional equivalence test, make some bugfixes and perf opts to the emitter.
* Final changes as requested by Kevin, code cleanup, add support for formal cells.
Diffstat (limited to 'src/main/scala/firrtl/transforms')
| -rw-r--r-- | src/main/scala/firrtl/transforms/CombineCats.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/CombineCats.scala b/src/main/scala/firrtl/transforms/CombineCats.scala index 71ef34bf..f89d03ce 100644 --- a/src/main/scala/firrtl/transforms/CombineCats.scala +++ b/src/main/scala/firrtl/transforms/CombineCats.scala @@ -63,11 +63,11 @@ class CombineCats extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(passes.RemoveValidIf), - Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency(firrtl.passes.SplitExpressions) ) - override def optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation]) + override def optionalPrerequisites = + Seq(Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency[firrtl.transforms.ConstantPropagation]) override def optionalPrerequisiteOf = Seq(Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter]) |