Remove some warnings (#2448)

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

4 files changed, 10 insertions, 10 deletions

diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
index 3f497c91..f2dffc4c 100644
--- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
+++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
@@ -171,7 +171,7 @@ class FlattenRegUpdate extends Transform with DependencyAPIMigration {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform]
+      Dependency[LegalizeClocksAndAsyncResetsTransform]
     )
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala
index ae110414..c2a79d53 100644
--- a/src/main/scala/firrtl/transforms/GroupComponents.scala
+++ b/src/main/scala/firrtl/transforms/GroupComponents.scala
@@ -336,13 +336,6 @@ class GroupComponents extends Transform with DependencyAPIMigration {
     }
     def onStmt(stmt: Statement): Unit = stmt match {
       case w: WDefInstance =>
-      case h: IsDeclaration =>
-        bidirGraph.addVertex(h.name)
-        h.map(onExpr(WRef(h.name)))
-      case Attach(_, exprs) => // Add edge between each expression
-        exprs.tail.map(onExpr(getWRef(exprs.head)))
-      case Connect(_, loc, expr) =>
-        onExpr(getWRef(loc))(expr)
       case q @ Stop(_, _, clk, en) =>
         val simName = simNamespace.newTemp
         simulations(simName) = q
@@ -351,6 +344,13 @@ class GroupComponents extends Transform with DependencyAPIMigration {
         val simName = simNamespace.newTemp
         simulations(simName) = q
         (args :+ clk :+ en).map(onExpr(WRef(simName)))
+      case h: IsDeclaration =>
+        bidirGraph.addVertex(h.name)
+        h.map(onExpr(WRef(h.name)))
+      case Attach(_, exprs) => // Add edge between each expression
+        exprs.tail.map(onExpr(getWRef(exprs.head)))
+      case Connect(_, loc, expr) =>
+        onExpr(getWRef(loc))(expr)
       case Block(stmts) => stmts.foreach(onStmt)
       case ignore @ (_: IsInvalid | EmptyStmt) => // do nothing
       case other => throw new Exception(s"Unexpected Statement $other")
diff --git a/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala b/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
index 24c792d7..16e148ca 100644
--- a/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
+++ b/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
@@ -97,7 +97,7 @@ class InlineAcrossCastsTransform extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Seq.empty
 
   override def invalidates(a: Transform): Boolean = a match {
-    case _: LegalizeClocksTransform => true
+    case _: LegalizeClocksAndAsyncResetsTransform => true
     case _ => false
   }
 
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 69d4aa8d..6e2c9a4a 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -38,7 +38,7 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform],
+      Dependency[LegalizeClocksAndAsyncResetsTransform],
       Dependency[FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup)
     )