blob: 69d4aa8ddc647dcf77d11bcb784489eb2013a657 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
// SPDX-License-Identifier: Apache-2.0
package firrtl.transforms
import firrtl._
import firrtl.Utils.v_keywords
import firrtl.options.Dependency
/** Transform that removes collisions with reserved keywords
* @param keywords a set of reserved words
*/
class RemoveKeywordCollisions(keywords: Set[String]) extends ManipulateNames {
private val inlineDelim = "_"
/** Generate a new name, by appending underscores, that will not conflict with the existing namespace
* @param n a name
* @param ns a [[Namespace]]
* @return Some name if a rename occurred, None otherwise
* @note prefix uniqueness is not respected
*/
override def manipulate = (n: String, ns: Namespace) =>
keywords.contains(n) match {
case true => Some(Namespace.findValidPrefix(n + inlineDelim, Seq(""), ns.cloneUnderlying ++ keywords))
case false => None
}
}
/** Transform that removes collisions with Verilog keywords */
class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
Seq(
Dependency[BlackBoxSourceHelper],
Dependency[FixAddingNegativeLiterals],
Dependency[ReplaceTruncatingArithmetic],
Dependency[InlineBitExtractionsTransform],
Dependency[InlineAcrossCastsTransform],
Dependency[LegalizeClocksTransform],
Dependency[FlattenRegUpdate],
Dependency(passes.VerilogModulusCleanup)
)
override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
override def optionalPrerequisiteOf = Seq.empty
}
|
