Remove some warnings (#2448)

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

11 files changed, 18 insertions, 16 deletions

diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala
index 90e38beb..de9ff523 100644
--- a/src/main/scala/firrtl/AddDescriptionNodes.scala
+++ b/src/main/scala/firrtl/AddDescriptionNodes.scala
@@ -151,7 +151,7 @@ class AddDescriptionNodes extends Transform with DependencyAPIMigration {
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.PropagatePresetAnnotations],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup),
       Dependency[firrtl.transforms.VerilogRename],
diff --git a/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala b/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
index a5f7f81f..6c6c0b69 100644
--- a/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
+++ b/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
@@ -880,6 +880,8 @@ private[firrtl] class RtlilEmitter extends SeqTransform with Emitter with Depend
               println("Leaving memory uninitialized.")
             case MemoryFileInlineInit(_, _) =>
               throw EmitterException(s"Memory $name cannot be initialized from a file, RTLIL cannot express this.")
+            case MemoryNoInit =>
+            // No initialization to emit
           }
           for (r <- rd) {
             val data = memPortField(x, r, "data")
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
index 03dcf0a3..3ca862b9 100644
--- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
+++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
@@ -33,7 +33,7 @@ object VerilogModulusCleanup extends Pass {
       Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate]
     )
 
diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala
index 9499889a..2bd17519 100644
--- a/src/main/scala/firrtl/passes/VerilogPrep.scala
+++ b/src/main/scala/firrtl/passes/VerilogPrep.scala
@@ -29,7 +29,7 @@ object VerilogPrep extends Pass {
       Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup),
       Dependency[firrtl.transforms.VerilogRename]
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index ab1cf7bb..057f85a6 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -204,6 +204,6 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
     val renames = MutableRenameMap()
     renames.setCircuit(c.main)
     val result = c.copy(modules = c.modules.map(onModule(renames)))
-    CircuitState(result, outputForm, state.annotations, Some(renames))
+    state.copy(circuit = result, renames = Some(renames))
   }
 }
diff --git a/src/main/scala/firrtl/stage/Forms.scala b/src/main/scala/firrtl/stage/Forms.scala
index 44ad25cd..f36e8f87 100644
--- a/src/main/scala/firrtl/stage/Forms.scala
+++ b/src/main/scala/firrtl/stage/Forms.scala
@@ -112,7 +112,7 @@ object Forms {
         Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
         Dependency[firrtl.transforms.InlineBitExtractionsTransform],
         Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-        Dependency[firrtl.transforms.LegalizeClocksTransform],
+        Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
         Dependency[firrtl.transforms.FlattenRegUpdate],
         Dependency(passes.VerilogModulusCleanup),
         Dependency[firrtl.transforms.VerilogRename],
diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
index 3f497c91..f2dffc4c 100644
--- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
+++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
@@ -171,7 +171,7 @@ class FlattenRegUpdate extends Transform with DependencyAPIMigration {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform]
+      Dependency[LegalizeClocksAndAsyncResetsTransform]
     )
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala
index ae110414..c2a79d53 100644
--- a/src/main/scala/firrtl/transforms/GroupComponents.scala
+++ b/src/main/scala/firrtl/transforms/GroupComponents.scala
@@ -336,13 +336,6 @@ class GroupComponents extends Transform with DependencyAPIMigration {
     }
     def onStmt(stmt: Statement): Unit = stmt match {
       case w: WDefInstance =>
-      case h: IsDeclaration =>
-        bidirGraph.addVertex(h.name)
-        h.map(onExpr(WRef(h.name)))
-      case Attach(_, exprs) => // Add edge between each expression
-        exprs.tail.map(onExpr(getWRef(exprs.head)))
-      case Connect(_, loc, expr) =>
-        onExpr(getWRef(loc))(expr)
       case q @ Stop(_, _, clk, en) =>
         val simName = simNamespace.newTemp
         simulations(simName) = q
@@ -351,6 +344,13 @@ class GroupComponents extends Transform with DependencyAPIMigration {
         val simName = simNamespace.newTemp
         simulations(simName) = q
         (args :+ clk :+ en).map(onExpr(WRef(simName)))
+      case h: IsDeclaration =>
+        bidirGraph.addVertex(h.name)
+        h.map(onExpr(WRef(h.name)))
+      case Attach(_, exprs) => // Add edge between each expression
+        exprs.tail.map(onExpr(getWRef(exprs.head)))
+      case Connect(_, loc, expr) =>
+        onExpr(getWRef(loc))(expr)
       case Block(stmts) => stmts.foreach(onStmt)
       case ignore @ (_: IsInvalid | EmptyStmt) => // do nothing
       case other => throw new Exception(s"Unexpected Statement $other")
diff --git a/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala b/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
index 24c792d7..16e148ca 100644
--- a/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
+++ b/src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala
@@ -97,7 +97,7 @@ class InlineAcrossCastsTransform extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Seq.empty
 
   override def invalidates(a: Transform): Boolean = a match {
-    case _: LegalizeClocksTransform => true
+    case _: LegalizeClocksAndAsyncResetsTransform => true
     case _ => false
   }
 
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 69d4aa8d..6e2c9a4a 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -38,7 +38,7 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform],
+      Dependency[LegalizeClocksAndAsyncResetsTransform],
       Dependency[FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup)
     )
diff --git a/src/main/scala/logger/LoggerOptions.scala b/src/main/scala/logger/LoggerOptions.scala
index bfd072df..e493a252 100644
--- a/src/main/scala/logger/LoggerOptions.scala
+++ b/src/main/scala/logger/LoggerOptions.scala
@@ -32,7 +32,7 @@ class LoggerOptions private[logger] (
   }
 
   /** Return the name of the log file, defaults to `a.log` if unspecified */
-  def getLogFileName(): Option[String] = if (!logToFile()) None else logFileName.orElse(Some("a.log"))
+  def getLogFileName(): Option[String] = logFileName.orElse(Some("a.log"))
 
   /** True if a [[Logger]] should be writing to a file */
   @deprecated("logToFile was removed, use logFileName.nonEmpty", "FIRRTL 1.2")