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path: root/src/main/scala/firrtl/passes
AgeCommit message (Expand)Author
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
2020-04-06Avoid using deprecated 'Gender' objectsAlbert Magyar
2020-03-26Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)Chick Markley
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
2020-03-16Check for module name conflictsAlbert Magyar
2020-03-13Make InlineInstances invalidate ResolveKindsJack Koenig
2020-03-12Avoid generating out-of-bounds indices in ReplaceAccessesAlbert Magyar
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-03-11Remove dead passes.DeadCodeElimination code (#1440)Albert Magyar
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
2020-03-03Fix error message for NegWidthException (#1418)Albert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings (#1...Albert Magyar
2019-10-03Add Block factory from argument list of Statements (#1197)Albert Magyar
2019-10-01Restore ResolveGenders to its status as a Pass (#1192)Jack Koenig
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-19Faster inline renaming (#1184)Albert Chen
2019-09-17Speed up InlineInstances (#1182)Jack Koenig
2019-09-16Deprecate Gender and add implicit Flow conversionSchuyler Eldridge
2019-09-16Rename gender to flowSchuyler Eldridge
2019-09-12update inline transform and testcasesAbert Chen
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
2019-08-09Remove unused CheckHighFormLike.IllegalChirrtlMemException (#1151)Albert Magyar
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-08-07DRY check chirrtl (#1148)Albert Magyar
2019-08-01Followup to PR #1142chick
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
2019-05-29make analog attachment order fixed with linked hash map (#1089)harrisonliew
2019-05-04Use UnknownKind instead misrepresented NodeKind (#1076)Leway Colin
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-03-26Convert the RemoveAccesses object into a class. (#1058)Jim Lawson
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
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