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path: root/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
AgeCommit message (Expand)Author
2023-02-03Fix invalid references generated by VerilogMemDelays (#2588)Alan L
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-16Rename gender to flowSchuyler Eldridge
2019-07-08Remove some warnings (#1118)Leway Colin
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-01fix bug. remove spurious connect that reassigns node (#358)Scott Beamer
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-23Fix bitmask (#346)Angie Wang
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