diff options
| author | Schuyler Eldridge | 2020-04-21 22:41:23 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-04-22 18:46:31 -0400 |
| commit | 39d76a02785f4391b67abd3b7d7720d287736312 (patch) | |
| tree | e820790206a46a315e0b2d5634c5a8c9825931a2 /src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | |
| parent | 1bf80040825e96ce04c15374304c144b9d48e902 (diff) | |
Mixin DependencyAPIMigration to all Transforms
This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index e5e6d6d4..3da4c391 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -168,7 +168,7 @@ class MemDelayAndReadwriteTransformer(m: DefModule) { object VerilogMemDelays extends Pass { - override val prerequisites = firrtl.stage.Forms.LowForm :+ Dependency(firrtl.passes.RemoveValidIf) + override def prerequisites = firrtl.stage.Forms.LowForm :+ Dependency(firrtl.passes.RemoveValidIf) override val dependents = Seq( Dependency[VerilogEmitter], |