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path: root/src/main/scala/firrtl/passes/memlib/ToMemIR.scala
AgeCommit message (Collapse)Author
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
* Stop ignoring read-under-write (RUW) parameter * Add conservative check: blackbox only when RUW is "undefined" * VerilogMemDelays now throws InternalError for read-first memories * Previously, read-first mems were incorrectly implemented as write-first
2019-02-01Mem helpers (#1010)Albert Magyar
* Add memory WRef factory for completeness * Refactor DefAnnotatedMemory construction for clarity
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
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