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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Previously, mems marked no dedup would prevent mems with the same
instance name in other modules from deduping
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[skip formal checks] LEC passes with Formality
* Improve code generation for smem RW-port wmode port
A common case for these port-enables is
wen = valid & write
ren = valid & !write
which the RW-port transform currently turns into
en = (valid & write) | (valid & !write)
wmode = valid & write
because it proved `wen` and `ren` are mutually exclusive via `write`.
Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression. In this case:
en = (valid & write) | (valid & !write)
wmode = write
* In RemoveCHIRRTL, infer mask relative to port definition
Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.
Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.
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but not Emitter. (#717)
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This allows the replseqmem transform to not deduplicate
some memories, based on their name.
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duplcate memory detection should be in circuit-level, not in module-level
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* Reorganized memory blackboxing
Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala
* Fixed tests to pass
* Use DefAnnotatedMemory instead of AppendableInfo
* Broke passes up into simpler passes
AnnotateMemMacros ->
(ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
(RenameAnnotatedMemoryPorts, ResolveMemoryReference)
* Fixed to make tests run
* Minor changes from code review
* Removed vim comments and renamed ReplSeqMem
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