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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add sbt-scalafix
* Add scalafix guide to README
* Remove Unused Import
* Remove deprecated procedure syntax
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Abstracts away option writing such that users no longer have to
understand scopt semantics. This adds a ShellOption class and a
HasShellOptions trait for something which provides one or more
ShellOptions. This refactors the FIRRTL codebase to use this style of
option specification.
Adds and uses DeletedWrapper to automatically generate
DeletedAnnotations.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds FirrtlStage, a reimplementation of the original FIRRTL
Driver as a Stage. This updates the original firrtl.options package to
implement FirrtlStage (namely, TransformLike is added) along with
FirrtlMain. Finally, the original FIRRTL Driver is converted to a
compatibility wrapper around FirrtlStage.
For background, Stage and Phase form the basis of the Chisel/FIRRTL
Hardware Compiler Framework (HCF). A Phase is a class that performs a
mathematical transformation on an AnnotationSeq (in effect, a
generalization of a FIRRTL transform). Curtly, a Stage is a Phase that
also provides a user interface for generating annotations. By their
construction, Phases are designed to be composed sequentially into a
transformation pipeline.
This modifies the existing options package (which provides
Stage/Phase) to build out a type hierarchy around Stage/Phase. This
adds TransformLike[A] which implements a mathematical transformation
over some type A. Additionally, and as an interface between different
TransformLikes, this adds Translator[A, B] which extends
TransformLike[A], but does an internal transformation over type B.
This is used to interface Phases with the existing FIRRTL compiler.
This adds a runTransform method to Phase that, like
Transform.runTransform, will automatically detect deleted Annotations
and generate DeletedAnnotations.
The new FirrtlStage, a reimplementation of FIRRTL's Driver, is added
as a Stage composed of the following Phases:
1. AddDefaults - add default annotations
2. AddImplicitEmitter - adds an implicit emitter derived from the
compiler
3. Checks - sanity check the AnnotationSeq
4. AddCircuit - convert FIRRTL input files/sources to circuits
5. AddImplicitOutputFile - add a default output file
6. Compiler - run the FIRRTL compiler
7. WriteEmitted - write any emitted modules/circuits to files
The Driver is converted to a compatibility layer that replicates old
Driver behavior. This is implemented by first using new toAnnotation
methods for CommonOptions and FirrtlExecutionOptions that enable
AnnotationSeq generation. Second, the generated AnnotationSeq is
preprocessed and sent to FirrtlStage. The resulting Phase order is
then:
1. AddImplicitAnnotationFile - adds a default annotation file
2. AddImplicitFirrtlFile - adds a default FIRRTL file using top name
3. AddImplicitOutputFile - adds an output file from top name
4. AddImplicitEmitter - adds a default emitter derived from a
compiler and any split modules command line option
5. FirrtlStage - the aforementioned new FirrtlStage
Finally, the output AnnotationSeq is then viewed as a
FirrtlExecutionResult. This compatibility layer enables uninterrupted
usage of old Driver infrastructure, e.g., FirrtlExecutionOptions and
CommonOptions can still be mutated directly and used to run the
Driver.
This results in differing behavior between the new FirrtlStage and the
old Driver, specifically:
- FirrtlStage makes a clear delineation between a "compiler" and an
"emitter". These are defined using separate options. A compiler is
"-X/--compiler", while an emitter is one of "-E/--emit-circuit" or
"-e/--emit-modules".
- Related to the above, the "-fsm/--split-modules" has been removed
from the FirrtlStage. This option is confusing once an implicit
emitter is removed. It is also unclear how this should be handled
once the user can specify multiple emitters, e.g., which emitter
should "--split-modules" apply to?
- WriteOutputAnnotations will, by default, not write
DeletedAnnotations to the output file.
- The old top name ("-tn/--top-name") option has been removed from
FirrtlStage. This option is really a means to communicate what
input and output files are as opposed to anything associated with
the circuit name. This option is preserved for the Driver
compatibility layer.
Additionally, this changes existing transform scheduling to work for
emitters (which subclass Transform). Previously, one emitter was
explicitly scheduled at the end of all transforms for a given
compiler. Additional emitters could be added, but they would be
scheduled as transforms. This fixes this to rely on transform
scheduling for all emitters. In slightly more detail:
1. The explicit emitter is removed from Compiler.compile
2. An explicit emitter is added to Compiler.compileAndEmit
3. Compiler.mergeTransforms will schedule emitters as late as
possible, i.e., all emitters will occur after transforms that
output their input form.
4. All AddImplicitEmitter phases (DriverCompatibility and normal)
will add RunFirrtlTransformAnnotations to add implicit emitters
The FIRRTL fat jar utilities are changed to point at FirrtlStage and not
at the Driver. This has backwards incompatibility issues for users
that are using the utilities directly, e.g., Rocket Chip.
The Logger has been updated with methods for setting options based on
an AnnotationSeq. This migrates the Logger to use AnnotationSeq as
input parameters, e.g., for makeScope. Old-style methods are left in
place and deprecated. However, the Logger is not itself a Stage.
The options of Logger Annotations are included in the base Shell and
Stage is updated to wrap its Phases in a Logger scope.
Additionally, this changes any code that does option parsing to always
prepend an annotation as opposed to appending an annotation. This is
faster, but standardizing on this has implications for dealing with
the parallel compilation annotation ordering.
A Shell will now put the initial annotations first (in the order the
user specified) and then place all annotations generating from parsing
after that. This adds a test case to verify this behavior.
Discovered custom transforms (via `RunFirrtlTransformAnnotation`s) are
discovered by the compiler phase in a user-specified order, but are
stored in reverse order to more efficiently prepend (as opposed to
append) to a list. This now reverses the transform order before
execution to preserve backwards compatibility of custom transform
ordering.
The Compiler phase also generates one deleted annotation for each
`RunFirrtlTransformAnnotation`. These are also reversed.
Miscellaneous small changes:
- Split main method of Stage into StageMain class
- Only mix in HasScoptOptions into Annotation companion objects (h/t
@jackkoenig)
- Store Compiler in CompilerAnnotation
- CompilerNameAnnotation -> CompilerAnnotation
- Make Emitter abstract in outputSuffix (move out of FirrtlOptions)
- Add DriverCompatibility.AddImplicitOutputFile that will add an
output file annotation based on the presence of a
TopNameAnnotation. This is important for compatibility with the
old Driver.
- Cleanup Scaladoc
- Refactor CircuitOption to be abstract in "toCircuit" that converts
the option to a FirrtlCircuitAnnotation. This allows more of the
conversion steps to be moved out of AddCircuit and into the actual
annotation.
- Add WriteDeletedAnnotation to module WriteOutputAnnotations
- A method for accessing a FirrtlExecutionResultView is exposed in
FIRRTL's DriverCompatibilityLayer
- Using "--top-name/-tn" or "--split-modules/-fsm" with FirrtlStage
generates an error indicating that this option is no longer
supported
- Using FirrtlStage without at least one emitter will generate a
warning
- Use vals for emitter in Compiler subclasses (these are used to
build RunFirrtlTransformAnnotations and the object should be
stable for comparisons)
- Fixes to tests that use LowTransformSpec instead of
MiddleTransformSpec. (SimpleTransformSpec is dumb and won't
schedule transforms correctly. If you rely on an emitter, you need
to use the right transform spec to test your transform if you're
relying on an emitter.)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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[skip formal checks] LEC passes with Formality
* Improve code generation for smem RW-port wmode port
A common case for these port-enables is
wen = valid & write
ren = valid & !write
which the RW-port transform currently turns into
en = (valid & write) | (valid & !write)
wmode = valid & write
because it proved `wen` and `ren` are mutually exclusive via `write`.
Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression. In this case:
en = (valid & write) | (valid & !write)
wmode = write
* In RemoveCHIRRTL, infer mask relative to port definition
Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.
Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
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update uses
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
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* fix imports in InferReadWrite
* improve reference & name resolution in ReplSeqMem
* add comments
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* toBitMask cat direction should be consistent with data
* minor comment updates
* moved remaining mem passes/utils to memlib
* changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
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