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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* remove all deprecations, switch to new API.
* Add MemLibOutConfigFileAnnotation to replace ConfWriter.
* Inline CreateMemoryAnnotations in ReplSeqMem.
* Dont use ConfWriter anymore.
* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.
* Fix for review.
0. Since DependencyAPI only initiate transform only once, ListBuffer is
dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
MemLibOutConfigFileAnnotation also extends from which now.
* Use two annotations converting and storing DefMemory.
0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform
* Fix for review.
0. replace AnnotatedMemoriesCollectorAnnotation with immutable
AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.
* private functions in ReplaceMemMacros transform.
* scalafmt
* remove ConfWriter API.
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