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2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2016-01-16WIP getting through testsazidar
2016-01-16WIPazidar
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-08-31Updated specazidar
2015-08-26Updated todoazidar
2015-08-24Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵azidar
now be small examples, categorized by either passes, errors, or features.
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-21Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-21Updated TODOazidar
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-06Updated todoazidar
2015-07-02Fixed performance bugs, runs 7x fasterazidar
2015-07-01Updated TODO.azidar
2015-06-30Updated TODO. Ran spelling/grammar check on specazidar
2015-06-22Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessorsazidar
2015-06-12Added more changes to specazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵azidar
low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates ↵azidar
reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable ↵azidar
plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵azidar
Should show up with check passes
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check ↵azidar
types. Does not compile
2015-05-04Added new stanzaazidar
2015-05-04Added a few more error checks. Not tested yet. Fixed bug in pad type inferenceazidar
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-01Fixed bug where the enable was looked at for lowering MUX.azidar
2015-04-29Made temp name generation counter, as well as the name, based off the ↵azidar
eventual named assignment. Should be very clear what caused the generation of the temp, and the numbering is based off of that cause, not a global counter
2015-04-29Added dshl and dshrazidar
2015-04-28Updated todoazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. ↵azidar
chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-27Added on-resetazidar
2015-04-24Merged TODOazidar
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
Conflicts: TODO src/main/stanza/passes.stanza
2015-04-24Updated TODO. Added backwards with prop for as and bitsazidar