diff options
| author | azidar | 2015-08-24 10:58:49 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 10:58:49 -0700 |
| commit | 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 (patch) | |
| tree | b8a4d9fc9b2063703a5f37fec538f7a220cc7681 /TODO | |
| parent | 02a7fb53fc424346a1693f23661a1b1a4a867c4f (diff) | |
Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 10 |
1 files changed, 2 insertions, 8 deletions
@@ -1,14 +1,9 @@ Support ASIC backend - Writemasks for ram's in general (ASICs and FPGAs) + Pass to generate writemasks for ram's in general (ASICs and FPGAs) Mem of vec, should just work? ASIC rams (pass to replace smem with black box) Readwrite Port -Readenables need work - - - - ================================================ ========== ADAM's BIG ARSE TODO LIST ============ ================================================ @@ -16,8 +11,8 @@ Readenables need work ======== Current Tasks ======== put clocks on accessors add clock check to high firrtl check -registers in onreset cannot have flips add equivalence to spec + remove SInt from bit/bits in spec naming still doesn't work - x!0 will conflict with x think about inferring read enable from lo firrtl @@ -30,7 +25,6 @@ Tests: Large width of dshl fix expand-whens to have correct semantics -update high/low firrtl checks need an annotation example move width inference earlier (required for consistent vec width inference) Temp elimination needs to count # uses |