From 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 24 Aug 2015 10:58:49 -0700
Subject: Removed old chisel3 tests that all failed for syntax reasons. Tests
 should now be small examples, categorized by either passes, errors, or
 features.

---
 TODO | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

(limited to 'TODO')

diff --git a/TODO b/TODO
index ed551b11..9a0ae987 100644
--- a/TODO
+++ b/TODO
@@ -1,14 +1,9 @@
 Support ASIC backend
-   Writemasks for ram's in general (ASICs and FPGAs)
+   Pass to generate writemasks for ram's in general (ASICs and FPGAs)
      Mem of vec, should just work?
    ASIC rams (pass to replace smem with black box)
    Readwrite Port
 
-Readenables need work
-
-
-
-
 ================================================
 ========== ADAM's BIG ARSE TODO LIST ============
 ================================================
@@ -16,8 +11,8 @@ Readenables need work
 ======== Current Tasks ========
 put clocks on accessors
 add clock check to high firrtl check
-registers in onreset cannot have flips
 add equivalence to spec
+
 remove SInt from bit/bits in spec
 naming still doesn't work - x!0 will conflict with x
 think about inferring read enable from lo firrtl
@@ -30,7 +25,6 @@ Tests:
    Large width of dshl
 
 fix expand-whens to have correct semantics
-update high/low firrtl checks
 need an annotation example
 move width inference earlier (required for consistent vec width inference)
 Temp elimination needs to count # uses
-- 
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