Updated firrtl for its passes to be a bit more modular, and to enable plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.

1 files changed, 24 insertions, 10 deletions

diff --git a/TODO b/TODO
index 9a4e7afc..8181a9ad 100644
--- a/TODO
+++ b/TODO
@@ -3,10 +3,9 @@
 ================================================
 
 ======== Current Tasks ========
-Declared references needs to understand scope
+Declared references needs to understand scope <= check in high form check
 Size of vector type must be non-negative
 Check for recursively defined instances
-Update spec
 <>
 Add Unit Tests for each pass
    Separate passes into discrete chunks
@@ -14,10 +13,30 @@ Add Unit Tests for each pass
    Check after each pass
    write test that checks instance types are correctly lowered
 move width inference earlier
-Register should be a NODE, not a wire that is connected to, because you shouldn't be able to write to a wire that was connected to a Register? hmm.. think about this
+Remove Pad
+Fix all primops and width inference
+Verilog
+SeqMem
+BlackBoxes
+Scaling
+
+======== Verilog Backend Notes ========
+1) Emit module. No Parameters. Include clk and reset signals
+2) Emit all declarations (wires,regs)
+3) Initialize all regs with random values under synthesis
+4) Emit all connections as assign statements
+5) Emit assertions under always @ posedge clk, under synthesisp
+6) Emit all register updates:
+      if(io_update_valid) begin
+         R4 <= io_update_bits_target;
+      end
+   Note: muxes turn into if/else statements within the always@ block
+Notes:
+   For now, emit mems as reg with nothing else.
+   WritePorts?
+
    
 ======== Update Core ==========
-Add source locaters
 Add exmodule
 Add vptype
 Add readwriteport
@@ -65,12 +84,7 @@ Verilog backend
 Eliminate skips
 
 ======== Consultations ========
-Stephen:
-   width equality
-      pin stephen on an example
-Patrick: 
-   move Infer-Widths to before vec expansion?
-   talk about primops
+Andrew: Way to keep Array information for backends to avoid code explosion
 
 ======== Think About ========
 <>