| Age | Commit message (Expand) | Author |
|---|
| 2016-01-16 | Made create-exps a bit faster | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | Added performance tests | azidar |
| 2015-11-24 | In process of adding FAME-1 transformation, updated todos in grammar file, up... | jackkoenig |
| 2015-10-27 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-10-19 | Merge pull request #47 from jackkoenig/master | Adam Izraelevitz |
| 2015-10-15 | Added infer-types pass, seems to work. Added infer-types error checking, modi... | Jack |
| 2015-10-14 | Updated Makefile and README to be more friendly to Scala implementation | Jack |
| 2015-10-08 | Install Stanza as a dependency of anything that uses it | Palmer Dabbelt |
| 2015-10-06 | Added ability to test scala FIRRTL | Jack |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-08-26 | Added regression test | azidar |
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should no... | azidar |
| 2015-07-31 | Merge pull request #12 from ucb-bar/make-deps | Adam Izraelevitz |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-29 | Added installation for linux | Adam Izraelevitz |
| 2015-07-29 | Fix makefile dependences so make -j doesn't fail | Andrew Waterman |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-13 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to gene... | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
| 2015-04-15 | Finished flo backend. Restructured todo list | azidar |
| 2015-03-24 | With new stanza | azidar |
| 2015-03-18 | Finished expand accessors and lower to ground | azidar |
| 2015-02-24 | Rewrote README to include installation instructions and stanza justification.... | azidar |
| 2015-02-20 | Rewrote the initialize-register pass, now correctly implemented | azidar |
| 2015-02-19 | Added compiler flags to allow tests to select which passes they test. | azidar |
| 2015-02-18 | Added more testing infrastructre, and Makefile to build firrtl | azidar |
| 2015-02-18 | Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of IR... | azidar |
