Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

1 files changed, 1 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index b0c200d5..6eda3cc3 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,7 @@ units = ALUTop Datapath Control Core
 v     = $(addsuffix .fir.v, $(units))
 
 $(units): % :
-	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v
+	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c
 	scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
 
 done: