Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

56 files changed, 696 insertions, 338 deletions

diff --git a/Makefile b/Makefile
index b0c200d5..6eda3cc3 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,7 @@ units = ALUTop Datapath Control Core
 v     = $(addsuffix .fir.v, $(units))
 
 $(units): % :
-	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v
+	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c
 	scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
 
 done:
diff --git a/notes/alpha.txt b/notes/alpha.txt
new file mode 100644
index 00000000..0f245bf7
--- /dev/null
+++ b/notes/alpha.txt
@@ -0,0 +1,77 @@
+========= RENAME STRATEGY =========
+Special chars ~!@#$%^*-_+=?/ get renamed to _XX, where XX is a hex representation of the symbol
+
+a_x 
+=> 
+a_XXx
+
+a_XXx 
+=> 
+a_XXXXx
+
+This guarantees all symbols use a subset of the character set
+
+Now, I need to rename duplicate symbols, so:
+
+wire x
+when p
+  wire x
+
+=>
+
+wire x%0
+when p
+  wire x%1
+
+We know that all new symbols are unique because they use a special character
+At this point, all names are unique.
+
+-- Bundle Expansion --
+To deal with bundle expansion, use another different special character:
+
+wire x : {a,b}
+
+=>
+
+wire x#a
+wire x#b
+
+-- Vector Expansion --
+
+To deal with bundle expansion, use another different special character:
+
+wire x : UInt<1>[3]
+
+=>
+
+wire x$0 : UInt<1>
+wire x$1 : UInt<1>
+wire x$2 : UInt<1>
+
+-- Creating Temporaries --
+To deal with creating temporaries, use another different special character:
+
+node x = a + b * c
+=>
+node x!0 = b * c
+node x!1 = a + x!0
+node x = x!1
+
+Finally, to deal with backends that only use subsets of the special characters, do another rename step to remove special characters (must remove $ again!)
+
+ASCII Hex
+_ 5F __
+~ 7E _A
+! 21 _B
+@ 40 _C
+# 23 _D
+$ 24 _E
+% 25 _F
+^ 5E _G
+* 2A _H
+- 2D _I
++ 2B _J
+= 3D _K
+? 3F _L
+/ 2F _M
+
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index c458f1e1..b87c654e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -12,10 +12,11 @@ public defstruct StandardFlo <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardFlo) -> List<Pass> :
    to-list $ [
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       ;; TempElimination()
       ToWorkingIR()
-      ;; MakeExplicitReset()
       ResolveKinds()
       CheckKinds()
       InferTypes()
@@ -31,9 +32,8 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
       Inline()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      SpecialRename(`$,`::)
-      CheckHighForm(`::)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Flo(file(c))
    ]
@@ -42,7 +42,9 @@ public defstruct StandardVerilog <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardVerilog) -> List<Pass> :
    to-list $ [
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       TempElimination()
       ToWorkingIR()
       ;; MakeExplicitReset()
@@ -60,9 +62,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       Pad()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      SpecialRename(`$,`__)
-      CheckHighForm(`__)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Verilog(file(c))
    ]
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index 91732f22..4d63a173 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -14,7 +14,9 @@ public defstruct InstrumentedVerilog <: Compiler :
 public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
    to-list $ [
       WhenCoverage(args(c)[0],args(c)[1])
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       TempElimination()
       ToWorkingIR()
       ;; MakeExplicitReset()
@@ -31,8 +33,8 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
       InferWidths()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Verilog(file(c))
    ]
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index b92939d7..608b47d2 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -39,9 +39,8 @@ defpackage firrtl/errors :
 ; * Width sizes are positive
 ; * Primops have the correct number of arguments
 
-public defstruct CheckHighForm <: Pass :
-   sym : Symbol
-public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form{_,sym(b)}
+public defstruct CheckHighForm <: Pass 
+public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form
 public defmethod name (b:CheckHighForm) -> String : "High Form Check"
 public defmethod short-name (b:CheckHighForm) -> String : "high-form-check"
 
@@ -240,7 +239,7 @@ defn check-high-form-primop (e:DoPrim, errors:Vector<PassException>,info:FileInf
       BITS-SELECT-OP     : correct-num(1,2)
 
 ;--------------- Check High Form Pass -------------------
-public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : 
+public defn check-high-form (c:Circuit) -> Circuit : 
    val errors = Vector<PassException>()
 
    defn check-valid-loc (info:FileInfo,e:Expression) -> False :
@@ -334,7 +333,6 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit :
          map(check-high-form-t{info(p),_},type(p))
          map(check-high-form-w{info(p),_},type(p))
 
-      names[`reset] = true
       match(m) :
          (m:ExModule) : false
          (m:InModule) : check-high-form-s(body(m),names)
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index b9d2cee4..b37e974f 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -5,8 +5,11 @@ defpackage firrtl/ir2 :
 public defmulti info! (x:?) -> FileInfo
 public defmethod info! (x:?) : FileInfo()
 
-public val expand-delin = `$
-public val gen-delin = `#
+public val vector-expand-delin = `_
+public val bundle-expand-delin = `_
+public val scope-delin = `%
+public val temp-delin = `!
+public val inline-delin = `^
 
 public definterface PortDirection
 public val INPUT = new PortDirection
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index f844d7cc..99679cf6 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -9,10 +9,9 @@ defpackage firrtl/passes :
 
 ;============== Pass List ================
 public val standard-passes = to-list $ [
-   CheckHighForm(expand-delin)
+   CheckHighForm()
    TempElimination()
    ToWorkingIR()
-   ;MakeExplicitReset()
    ResolveKinds()
    CheckKinds()
    InferTypes()
@@ -282,6 +281,155 @@ defmethod map (f: Type -> Type, e: WSubfield) :
 defmethod map (f: Type -> Type, e: WIndex) :
    WIndex(exp(e), value(e), f(type(e)), gender(e))
 
+;================= Remove Special Characters ========================
+; Returns a new Circuit where all names have all special characters 
+;    removed, except _.
+
+public defstruct RemoveSpecialChars <: Pass
+public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars
+public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters"
+public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars"
+
+;------------ Helper Functions -------------
+
+defn get-new-string (n:Char) -> String :
+   switch {n == _} :
+      '_' : "__"
+      '~' : "_A"
+      '!' : "_B"
+      '@' : "_C"
+      '#' : "_D"
+      '$' : "_E"
+      '%' : "_F"
+      '^' : "_G"
+      '*' : "_H"
+      '-' : "_I"
+      '+' : "_J"
+      '=' : "_K"
+      '?' : "_L"
+      '/' : "_M"
+      else : to-string(n)
+
+;------------ Pass ------------------
+
+defn remove-special-chars (c:Circuit) :
+   defn rename (n:Symbol) -> Symbol :
+      val n* = Vector<String>()
+      for c in to-string(n) do :
+         add(n*,get-new-string(c))
+      symbol-join(n*)
+   defn rename-t (t:Type) -> Type :
+      match(map(rename-t,t)) :
+         (t:BundleType) : BundleType $
+            for f in fields(t) map :
+               Field(rename(name(f)),flip(f),type(f))
+         (e) : e
+   defn rename-e (e:Expression) -> Expression :
+      map{rename-t,_} $ match(map(rename-e,e)) :
+         (e:Ref) : Ref(rename(name(e)),type(e))
+         (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e))
+         (e) : e
+   defn rename-s (s:Stmt) -> Stmt :
+      map{rename-t,_} $ match(map(rename-e,s)) :
+         (s:DefWire) : DefWire(info(s),rename(name(s)),type(s))
+         (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s))
+         (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s))
+         (s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
+         (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s))
+         (s) : map(rename-s,s)
+
+   Circuit(info(c),modules*, main(c)) where :
+      val modules* =
+         for m in modules(c) map :
+            match(m) :
+               (m:InModule) : 
+                  val ports* = for p in ports(m) map :
+                     Port(info(p),rename(name(p)),direction(p),rename-t(type(p)))
+                  InModule(info(m),rename(name(m)), ports*, rename-s(body(m)))
+               (m:ExModule) : m
+
+;================= Remove Scopes ========================
+; Returns a new Circuit where duplicate names have been 
+;    renamed.
+
+public defstruct RemoveScopes <: Pass
+public defmethod pass (b:RemoveScopes) -> (Circuit -> Circuit) : remove-scopes
+public defmethod name (b:RemoveScopes) -> String : "Remove Scopes"
+public defmethod short-name (b:RemoveScopes) -> String : "rem-scopes"
+
+;------------ Helper Functions -------------
+
+defn lookup (n:Symbol, env:Vector<HashTable<Symbol,Int>>) -> Symbol : lookup(n,env,length(env) - 1)
+defn lookup (n:Symbol, env:Vector<HashTable<Symbol,Int>>, index:Int) -> Symbol :
+   if index < 0 : n
+   else :
+      if not key?(env[index],n) : lookup(n,env,index - 1)
+      else : symbol-join([n scope-delin (env[index])[n]])
+
+;------------ Pass ------------------
+
+defn remove-scopes (c:Circuit) :
+   defn remove-scopes (m:InModule) : 
+      val occurrences = HashTable<Symbol,Int>(symbol-hash)
+      val uses = HashTable<Symbol,Int>(symbol-hash)
+      defn rename (n:Symbol,env:Vector<HashTable<Symbol,Int>>) -> Symbol :
+         if occurrences[n] > 1 : 
+            val i = get?(uses,n,0)
+            uses[n] = i + 1
+            env[length(env) - 1][n] = i
+            symbol-join([n `% i])
+         else : n
+      defn build-s (s:Stmt) :
+         match(s) : 
+            (s:DefWire|DefRegister|DefInstance|DefMemory|DefNode|DefAccessor) : 
+               occurrences[name(s)] = get?(occurrences,name(s),0) + 1
+            (s) : do(build-s,s)
+      defn remove-scopes-e (e:Expression,env:Vector<HashTable<Symbol,Int>>) :
+         match(map(remove-scopes-e{_,env},e)) :
+            (e:Ref) : Ref(lookup(name(e),env),type(e))
+            (e) : e
+      defn remove-scopes-s (s:Stmt,env:Vector<HashTable<Symbol,Int>>) -> Stmt :
+         match(map(remove-scopes-e{_,env},s)) :
+            (s:DefWire) : DefWire(info(s),rename(name(s),env),type(s))
+            (s:DefRegister) : DefRegister(info(s),rename(name(s),env),type(s),clock(s),reset(s))
+            (s:DefInstance) : DefInstance(info(s),rename(name(s),env),module(s))
+            (s:DefMemory) : DefMemory(info(s),rename(name(s),env),type(s),seq?(s),clock(s))
+            (s:DefNode) : DefNode(info(s),rename(name(s),env),value(s))
+            (s:DefAccessor) : DefAccessor(info(s),rename(name(s),env),source(s),index(s),acc-dir(s))
+            (s:Conditionally) :
+               add(env,HashTable<Symbol,Int>(symbol-hash))
+               val conseq* = remove-scopes-s(conseq(s),env)
+               pop(env)
+
+               add(env,HashTable<Symbol,Int>(symbol-hash))
+               val alt* = remove-scopes-s(alt(s),env)
+               pop(env)
+               Conditionally(info(s),pred(s),conseq*,alt*)
+            (s) : map(remove-scopes-s{_,env},s)
+
+      ;build occurrences table
+      for p in ports(m) do :
+         occurrences[name(p)] = get?(occurrences,name(p),0) + 1
+      build-s(body(m))
+
+      ;rename
+      val env = Vector<HashTable<Symbol,Int>>()
+      add(env,HashTable<Symbol,Int>(symbol-hash))
+      val ports* = 
+         for p in ports(m) map :
+            Port(info(p),rename(name(p),env),direction(p),type(p))
+      val body* = remove-scopes-s(body(m),env)
+      
+      InModule(info(m),name(m), ports*, body*)
+
+   Circuit(info(c),modules*, main(c)) where :
+      val modules* =
+         for m in modules(c) map :
+            match(m) :
+               (m:InModule) : remove-scopes(m)
+               (m:ExModule) : m
+
 ;================= Temporary Variable Elimination ========================
 ; Returns a new Circuit where temporary variables are removed and returns
 ;   the resulting nested expression
@@ -771,18 +919,19 @@ defn index-of-elem (t:BundleType, s:Symbol) -> Int :
       error("Shouldn't be here")
 
 defn generate-entry (n:Symbol,t:Type) -> List<NTF> :
-   defn uniquify (n*:Symbol) -> Symbol : symbol-join([n expand-delin n*])
+   defn v-uniquify (n*:Symbol) -> Symbol : symbol-join([n vector-expand-delin n*])
+   defn b-uniquify (n*:Symbol) -> Symbol : symbol-join([n bundle-expand-delin n*])
    match(t) :
       (t:BundleType) : 
          for f in fields(t) map-append :
             val es = generate-entry(name(f),type(f))
             for e in es map :
-               NTF(uniquify(name(e)),type(e),flip(e) * flip(f))
+               NTF(b-uniquify(name(e)),type(e),flip(e) * flip(f))
       (t:VectorType) :
          for i in 0 to size(t) map-append :
             val es = generate-entry(to-symbol(i),type(t))
             for e in es map :
-               NTF(uniquify(name(e)),type(e),flip(e))
+               NTF(v-uniquify(name(e)),type(e),flip(e))
       (t) : list $ NTF(n,t,DEFAULT)
 
 defn expand-expr (e:Expression) -> List<EF> :
@@ -986,9 +1135,9 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
       DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
    defn get-name (e:Expression) -> Symbol :
       match(e) :
-         (e:WRef) : symbol-join([name(e) gen-delin])
-         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) gen-delin])
-         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) gen-delin])
+         (e:WRef) : symbol-join([name(e) temp-delin])
+         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) temp-delin])
+         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) temp-delin])
          (e) : `T
    match(s) :
       (s:ConnectToIndexed) : Begin $
@@ -1857,17 +2006,17 @@ defn inline-instances (c:Circuit) :
          (e:WSubfield) : 
             match(kind(exp(e) as WRef)) :
                (k:InstanceKind) : 
-                  WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e))
+                  WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e))
                (k:MemKind) : e
          (e) : e
-   defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n expand-delin ref])
+   defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n inline-delin ref])
    defn rename-e (e:Expression,n:Symbol) -> Expression :
       match(map(rename-e{_,n},e)) :
          (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e))
          (e:WSubfield) : 
             match(kind(exp(e) as WRef)) :
                (k:InstanceKind) : 
-                  WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e))
+                  WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e))
                (k:MemKind) : e
          (e) : e
    defn rename-s (s:Stmt,n:Symbol) -> Stmt :
@@ -1911,7 +2060,7 @@ defn split-exp (c:Circuit) :
                if not all-same-type? : 
                   val n* = 
                      if n typeof False : firrtl-gensym(`T,sh)
-                     else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh)
+                     else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh)
                   add(v,DefNode(info,n*,e))
                   WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
                else : e
@@ -1923,10 +2072,12 @@ defn split-exp (c:Circuit) :
          (s:Conditionally) : 
             add(v,map(split-exp-e{_,full-name(loc(conseq(s) as Connect)),info(s)},s))
             do(f,s)
-         (s:Connect) :
-            match(loc(s)) :
-               (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s))
-         (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s))
+         (s:Connect) : 
+            val exp* = map(split-exp-e{_,full-name(loc(s)),info(s)},exp(s))
+            add(v,Connect(info(s),loc(s),exp(s)))
+         (s:DefNode) : 
+            val exp* = map(split-exp-e{_,name(s),info(s)},value(s))
+            add(v,DefNode(info(s),name(s),exp*))
          (s) : add(v,map(split-exp-e{_,false,info(s)},s))
       false
 
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 23591f45..29112271 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -249,6 +249,7 @@ defn emit-module (m:InModule) :
          OUTPUT : 
             print-all([port-indent "output " get-width(type(p)) " " name(p) end])
             add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
+   if length(ports(m)) == 0 : print(");\n")
 
    for w in wires do :
       print("  ")
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 5725aa90..62eba530 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -4,5 +4,6 @@
 
 circuit Flip-Mem : 
   module Flip-Mem : 
-    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10]
-    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10]
+    input clk : Clock
+    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10], clk
+    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10], clk
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir
new file mode 100644
index 00000000..1d9f7ef6
--- /dev/null
+++ b/test/errors/high-form/RemoveScope.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+  module Top :
+    wire x : UInt<1>
+    node p = UInt(1)
+    when p :
+       wire x : UInt<1>
+       x := UInt(1)
+       node y = add(x,UInt(1))
+    else :
+       wire x : UInt<1>
+       x := UInt(1)
+       node z = add(x,UInt(1))
+    x := UInt(1)
+    node w = add(x,UInt(1))
diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir
new file mode 100644
index 00000000..f224ce68
--- /dev/null
+++ b/test/errors/high-form/SpecialChars.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+  module Top :
+    wire x : UInt<1>
+    x := UInt(1)
+    wire x~y : UInt<2>
+    x~y := UInt(1)
+    wire x!y : UInt<2>
+    x!y := UInt(1)
+    wire x@y : UInt<2>
+    x@y := UInt(1)
+    wire x#y : UInt<2>
+    x#y := UInt(1)
+    wire x%y : UInt<2>
+    x%y := UInt(1)
+    wire x^y : UInt<2>
+    x^y := UInt(1)
+    wire x*y : UInt<2>
+    x*y := UInt(1)
+    wire x-y : UInt<2>
+    x-y := UInt(1)
+    wire x_y : UInt<2>
+    x_y := UInt(1)
+    wire x+y : UInt<2>
+    x+y := UInt(1)
+    wire x=y : UInt<2>
+    x=y := UInt(1)
+    wire x?y : UInt<2>
+    x?y := UInt(1)
+    wire x/y : UInt<2>
+    x/y := UInt(1)
+
+
diff --git a/test/errors/high-form/WrongReset.fir b/test/errors/high-form/WrongReset.fir
deleted file mode 100644
index adeadee6..00000000
--- a/test/errors/high-form/WrongReset.fir
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-
-; CHECK: Module Top has a reset that is not of type UInt<1>.
-; CHECK: Module B has a reset that is not of type UInt<1>.
-; CHECK: Module C has a reset that is not of type UInt<1>.
-
-circuit Top :
-  module Top :
-    input reset : SInt<1>
-  module B :
-    input reset : UInt
-  module C :
-    output reset : UInt<1>
-
-
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
new file mode 100644
index 00000000..cbbb01f1
--- /dev/null
+++ b/test/features/TwoClocks.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk1 : Clock
+    input clk2 : Clock
+    input reset1 : UInt<1>
+    input reset2 : UInt<1>
+    reg src : UInt<10>, clk1, reset1
+    reg sink : UInt<10>, clk2, reset2
+
+    onreset src := UInt(0)
+    src := addw(src,UInt(1))
+
+    reg sync_A : UInt<10>, clk2, reset2
+    sync_A := src
+    reg sync_B : UInt<10>, clk2, reset2
+    sync_B := sync_A
+
+    sink := sync_B
+
+;CHECK: Done!
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index ea453ab1..38bd6fe5 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -4,27 +4,32 @@
 circuit top :
    module top :
       wire i : UInt
+      i := UInt(1)
       wire j : UInt
+      j := UInt(1)
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a$0$x : UInt<32>
-      ; CHECK: wire a$0$y : UInt<32>
-      ; CHECK: wire a$1$x : UInt<32>
-      ; CHECK: wire a$1$y : UInt<32>
+      a[0].x := UInt(1)
+      a[0].y := UInt(1)
+      a[1].x := UInt(1)
+      a[1].y := UInt(1)
+      ; CHECK: wire a_0_x : UInt<32>
+      ; CHECK: wire a_0_y : UInt<32>
+      ; CHECK: wire a_1_x : UInt<32>
+      ; CHECK: wire a_1_y : UInt<32>
+
 
       infer accessor b = a[i]
-      ; CHECK: wire b$x : UInt<32>
-      ; CHECK: wire b$y : UInt<32>
-      ; CHECK: b$x := a$0$x
-      ; CHECK: node i#0 = i
-      ; CHECK: when eq(i#0, UInt(1)) :
-      ; CHECK:    b$x := a$1$x      
-      ; CHECK: node i#1 = i
-      ; CHECK: when eq(i#1, UInt(0)) :
-      ; CHECK:    a$0$y := b$y      
-      ; CHECK: when eq(i#1, UInt(1)) :
-      ; CHECK:    a$1$y := b$y      
+      ; CHECK: wire b_x : UInt<32>
+      ; CHECK: wire b_y : UInt<32>
+      ; CHECK: b_x := a_0_x
+      ; CHECK: node i!0 = i
+      ; CHECK: when eq(i!0, UInt(1)) : b_x := a_1_x      
+      ; CHECK: node i!1 = i
+      ; CHECK: when eq(i!1, UInt(0)) : a_0_y := b_y      
+      ; CHECK: when eq(i!1, UInt(1)) : a_1_y := b_y      
       j := b.x
+      b.y := UInt(1)
       
 ; CHECK: Finished Expand Indexed Connects
 
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 261ebf02..10da47cf 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -2,7 +2,9 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : { x : UInt, flip y : UInt}
+      input clk : Clock
+      input reset : UInt<1>
+      reg r : { x : UInt, flip y : UInt},clk,reset
       wire a : UInt
       wire b : UInt
       wire w : { x : UInt, flip y : UInt}
@@ -13,7 +15,7 @@ circuit top :
       w.y := a
       r.x := a
       r.y := b
-      on-reset r := w
+      onreset r := w
 
 ; CHECK: when UInt(1) : r$x := mux(reset, w$x, a)
 ; CHECK: when UInt(1) : r$y := b
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 4d23a549..c81ca485 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -2,9 +2,11 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       wire q : UInt
-      reg r : UInt
+      reg r : UInt, clk, reset
       wire a : UInt
       wire b : UInt
       wire x : UInt
@@ -20,12 +22,12 @@ circuit top :
       z := UInt(1)
       w := UInt(1)
 
-      on-reset r := w
+      onreset r := w
       when p :
-        on-reset r := x
+        onreset r := x
         r := a
       when q :
-        on-reset r := y
+        onreset r := y
         r := b
       r := z
 ; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z)
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 4e6ea1e5..1332395c 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,16 +3,18 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      cmem m : UInt<1>[2]
+      input clk : Clock
+      input reset : UInt<1>
+      cmem m : UInt<1>[2], clk
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
       j := UInt(1)
-      reg r : UInt<1>
+      reg r : UInt<1>, clk, reset
 
       p := j
       when p :
-        on-reset r := i
+        onreset r := i
         infer accessor a = m[i] 
         i := a
         infer accessor b = m[i]
@@ -27,7 +29,7 @@ circuit top :
         p := i
         when e :
            p := p
-           on-reset r := p
+           onreset r := p
            r := p
         
 
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index 03b1f965..f752eccd 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -3,7 +3,9 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : UInt<1>[10]
+      input clk : Clock
+      input reset : UInt<1>
+      reg r : UInt<1>[10],clk,reset
       r[0] := UInt(1)
       r[1] := UInt(1)
       r[2] := UInt(1)
@@ -14,6 +16,6 @@ circuit top :
       r[7] := UInt(1)
       r[8] := UInt(1)
       r[9] := UInt(1)
-      on-reset r[3] := UInt(0)
+      onreset r[3] := UInt(0)
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 01347fdd..ac0f405b 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -1,9 +1,11 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
-      reg r : UInt
+      reg r : UInt,clk,reset
       when p :
          r := UInt(20)
 
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index 521e1710..ab6f4915 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -1,9 +1,11 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
-      reg r : UInt
+      reg r : UInt,clk,reset
       when p :
          on-reset r := UInt(10)
          r := UInt(20)
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index df6c7034..03f5ade9 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -1,10 +1,12 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
+         reg r : UInt,clk,reset
          r := UInt(20)
 
 ; CHECK: Expand Whens
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index ad191a01..1de6d8f4 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -1,11 +1,13 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
-         on-reset r := UInt(10)
+         reg r : UInt,clk,reset
+         onreset r := UInt(10)
          r := UInt(20)
 
 ; CHECK: Expand Whens
@@ -13,7 +15,7 @@ circuit top :
 ; CHECK: circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
-; CHECK:     reg r : UInt
+; CHECK:     reg r : UInt, clk, reset
 ; CHECK:     p := UInt(1)
 ; CHECK:     r := mux(reset, UInt(10), UInt(20))
 
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index d119932f..aec64871 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -1,11 +1,13 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
-         on-reset r := UInt(10)
+         reg r : UInt, clk, reset
+         onreset r := UInt(10)
          r := UInt(20)
 
 ; CHECK: Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index b6c98263..2203f25e 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,8 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      input clk : Clock
+      cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk
       wire i : UInt<1>
       i := UInt(1)
       wire p : UInt<1>
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index 6e407178..653a3e88 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -1,8 +1,9 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
       wire p : UInt
-      cmem m : UInt<4>[10]
+      cmem m : UInt<4>[10], clk
       p := UInt(1)
       when p :
          write accessor a = m[UInt(3)]
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 6bceda5c..735a69c9 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -6,30 +6,31 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z := sub-wrap(x, y)
-      ;CHECK: z@<t:UInt> := sub-wrap(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
+      z := subw(x, y)
+      ;CHECK: z@<t:UInt> := subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
 ; CHECK: reg x : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
       ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
-         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.z@<t:UInt>      
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
          s2.x := x
@@ -44,10 +45,14 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
       i.a := a
       i.b := b
+      i.clk := clk
+      i.reset := reset
       i.e := UInt(1)
       z := i.z
 
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 05e9adf8..61656e9c 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -51,17 +51,17 @@ circuit top :
       node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vadd-wrap = add-wrap(a, c)    ;CHECK: node vadd-wrap = add-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node wadd-wrap = add-wrap(a, b) ;CHECK: node wadd-wrap = add-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xadd-wrap = add-wrap(a, d) ;CHECK: node xadd-wrap = add-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node yadd-wrap = add-wrap(c, b) ;CHECK: node yadd-wrap = add-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
-      node zadd-wrap = add-wrap(c, d) ;CHECK: node zadd-wrap = add-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
-      node vsub-wrap = sub-wrap(a, c)    ;CHECK: node vsub-wrap = sub-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node wsub-wrap = sub-wrap(a, b) ;CHECK: node wsub-wrap = sub-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xsub-wrap = sub-wrap(a, d) ;CHECK: node xsub-wrap = sub-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node ysub-wrap = sub-wrap(c, b) ;CHECK: node ysub-wrap = sub-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
-      node zsub-wrap = sub-wrap(c, d) ;CHECK: node zsub-wrap = sub-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+      node vaddw = addw(a, c)    ;CHECK: node vaddw = addw(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node waddw = addw(a, b) ;CHECK: node waddw = addw(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node xaddw = addw(a, d) ;CHECK: node xaddw = addw(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
+      node yaddw = addw(c, b) ;CHECK: node yaddw = addw(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
+      node zaddw = addw(c, d) ;CHECK: node zaddw = addw(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+   
+      node vsubw = subw(a, c)    ;CHECK: node vsubw = subw(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node wsubw = subw(a, b) ;CHECK: node wsubw = subw(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node xsubw = subw(a, d) ;CHECK: node xsubw = subw(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
+      node ysubw = subw(c, b) ;CHECK: node ysubw = subw(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
+      node zsubw = subw(c, d) ;CHECK: node zsubw = subw(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
       node vlt = lt(a, c)    ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
@@ -103,13 +103,13 @@ circuit top :
       node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt>
       node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt>
    
-      node vas-UInt = as-UInt(d)   ;CHECK: node vas-UInt = as-UInt(d@<t:SInt>)@<t:UInt>
-      node was-UInt = as-UInt(a) ;CHECK: node was-UInt = as-UInt(a@<t:UInt>)@<t:UInt>
-      node zas-UInt = as-UInt(c) ;CHECK: node zas-UInt = as-UInt(c@<t:SInt>)@<t:UInt>
+      node vasUInt = asUInt(d)   ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt>
+      node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@<t:UInt>)@<t:UInt>
+      node zasUInt = asUInt(c) ;CHECK: node zasUInt = asUInt(c@<t:SInt>)@<t:UInt>
    
-      node vas-SInt = as-SInt(a)   ;CHECK: node vas-SInt = as-SInt(a@<t:UInt>)@<t:SInt>
-      node was-SInt = as-SInt(a) ;CHECK: node was-SInt = as-SInt(a@<t:UInt>)@<t:SInt>
-      node zas-SInt = as-SInt(c) ;CHECK: node zas-SInt = as-SInt(c@<t:SInt>)@<t:SInt>
+      node vasSInt = asSInt(a)   ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt>
+      node wasSInt = asSInt(a) ;CHECK: node wasSInt = asSInt(a@<t:UInt>)@<t:SInt>
+      node zasSInt = asSInt(c) ;CHECK: node zasSInt = asSInt(c@<t:SInt>)@<t:SInt>
    
       node vshl = shl(a, 10)   ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt>
       node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt>
@@ -127,23 +127,23 @@ circuit top :
       node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt>
       node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt>
    
-      node vconvert = convert(a)   ;CHECK: node vconvert = convert(a@<t:UInt>)@<t:SInt>
-      node wconvert = convert(a) ;CHECK: node wconvert = convert(a@<t:UInt>)@<t:SInt>
-      node zconvert = convert(c) ;CHECK: node zconvert = convert(c@<t:SInt>)@<t:SInt>
+      node vcvt = cvt(a)   ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt>
+      node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt>
+      node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt>
    
       node vneg = neg(a)   ;CHECK: node vneg = neg(a@<t:UInt>)@<t:UInt>
       node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:UInt>
       node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:UInt>
    
-      node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node vor = bit-or(a, b)  ;CHECK: node vor = bit-or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node wxor = bit-xor(a, b) ;CHECK: node wxor = bit-xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node uand = and(a, b) ;CHECK: node uand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node vor = or(a, b)  ;CHECK: node vor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@<t:UInt>, 0)@<t:UInt>
       node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
 
-      node uand-reduce = bit-and-reduce(a, b, a) ;CHECK: node uand-reduce = bit-and-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
-      node uor-reduce = bit-or-reduce(a, b, a) ;CHECK: node uor-reduce = bit-or-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
-      node uxor-reduce = bit-xor-reduce(a, b, a) ;CHECK: node uxor-reduce = bit-xor-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
 
 ;CHECK: Finished Infer Types
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 9e4bf0f5..efed25ad 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -35,10 +37,14 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
       i.a := a
       i.b := b
+      i.clk := clk
+      i.reset := reset
       i.e := UInt(1)
       z := i.z
 
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 6a50ae77..1b588c0e 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -3,9 +3,11 @@
 ;CHECK: Infer Widths
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire e : UInt<30>
       e := UInt(1)
-      reg y : UInt
+      reg y : UInt,clk,reset
       y := e
 
       wire a : UInt<20>
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index 2c76bc82..6227520d 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -35,10 +37,14 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
       i.a := a
       i.b := b
+      i.clk := clk
+      i.reset := reset
       i.e := UInt(1)
       z := i.z
 
diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index 562787a4..bc803e97 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -9,23 +9,23 @@ circuit ALUTop :
     input alu_op : UInt<4>
     
     node shamt = bits(B, 4, 0)
-    node T_157 = add-wrap(A, B)
-    node T_158 = sub-wrap(A, B)
-    node T_159 = convert(A)
+    node T_157 = addw(A, B)
+    node T_158 = subw(A, B)
+    node T_159 = cvt(A)
     node T_160 = dshr(T_159, shamt)
-    node T_161 = as-UInt(T_160)
+    node T_161 = asUInt(T_160)
     node T_162 = dshr(A, shamt)
     node T_163 = dshl(A, shamt)
     node T_164 = bits(T_163, 31, 0)
-    node T_165 = convert(A)
-    node T_166 = convert(B)
+    node T_165 = cvt(A)
+    node T_166 = cvt(B)
     node T_167 = lt(T_165, T_166)
-    node T_168 = as-UInt(T_167)
+    node T_168 = asUInt(T_167)
     node T_169 = lt(A, B)
-    node T_170 = as-UInt(T_169)
-    node T_171 = bit-and(A, B)
-    node T_172 = bit-or(A, B)
-    node T_173 = bit-xor(A, B)
+    node T_170 = asUInt(T_169)
+    node T_171 = and(A, B)
+    node T_172 = or(A, B)
+    node T_173 = xor(A, B)
     node T_174 = eq(UInt<4>(10), alu_op)
     node T_175 = mux(T_174, A, B)
     node T_176 = eq(UInt<4>(4), alu_op)
@@ -51,9 +51,9 @@ circuit ALUTop :
     node T_195 = bits(oot, 31, 0)
     out := T_195
     node T_196 = bit(alu_op, 0)
-    node T_197 = sub-wrap(UInt<1>(0), B)
+    node T_197 = subw(UInt<1>(0), B)
     node T_198 = mux(T_196, T_197, B)
-    node T_199 = add-wrap(A, T_198)
+    node T_199 = addw(A, T_198)
     sum := T_199
   module ALUdec : 
     input opcode : UInt<7>
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index 48af58b8..65efb47f 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -3,13 +3,15 @@
 circuit Counter : 
   module Counter : 
     input inc : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output tot : UInt<8>
     input amt : UInt<4>
     
-    reg T_13 : UInt<8>
-    on-reset T_13 := UInt<8>(0)
+    reg T_13 : UInt<8>,clk,reset
+    onreset T_13 := UInt<8>(0)
     when inc : 
-      node T_14 = add-wrap(T_13, amt)
+      node T_14 = addw(T_13, amt)
       node T_15 = gt(T_14, UInt<8>(255))
       node T_16 = mux(T_15, UInt<1>(0), T_14)
       T_13 := T_16
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index b9da2273..4e0387d0 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -3,17 +3,19 @@
 circuit EnableShiftRegister : 
   module EnableShiftRegister : 
     input in : UInt<4>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     
-    reg r0 : UInt<4>
-    on-reset r0 := UInt<4>(0)
-    reg r1 : UInt<4>
-    on-reset r1 := UInt<4>(0)
-    reg r2 : UInt<4>
-    on-reset r2 := UInt<4>(0)
-    reg r3 : UInt<4>
-    on-reset r3 := UInt<4>(0)
+    reg r0 : UInt<4>,clk,reset
+    onreset r0 := UInt<4>(0)
+    reg r1 : UInt<4>,clk,reset
+    onreset r1 := UInt<4>(0)
+    reg r2 : UInt<4>,clk,reset
+    onreset r2 := UInt<4>(0)
+    reg r3 : UInt<4>,clk,reset
+    onreset r3 := UInt<4>(0)
     when shift : 
       r0 := in
       r1 := r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index f45002f5..9baa05a6 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -4,17 +4,19 @@ circuit LFSR16 :
   module LFSR16 : 
     output out : UInt<16>
     input inc : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     
-    reg res : UInt<16>
-    on-reset res := UInt<16>(1)
+    reg res : UInt<16>,clk,reset
+    onreset res := UInt<16>(1)
     when inc : 
       node T_16 = bit(res, 0)
       node T_17 = bit(res, 2)
-      node T_18 = bit-xor(T_16, T_17)
+      node T_18 = xor(T_16, T_17)
       node T_19 = bit(res, 3)
-      node T_20 = bit-xor(T_18, T_19)
+      node T_20 = xor(T_18, T_19)
       node T_21 = bit(res, 5)
-      node T_22 = bit-xor(T_20, T_21)
+      node T_22 = xor(T_20, T_21)
       node T_23 = bits(res, 15, 1)
       node T_24 = cat(T_22, T_23)
       res := T_24
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 59352162..ca530ea2 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -5,10 +5,12 @@ circuit MemorySearch :
     input target : UInt<4>
     output address : UInt<3>
     input en : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output done : UInt<1>
     
-    reg index : UInt<3>
-    on-reset index := UInt<3>(0)
+    reg index : UInt<3>,clk,reset
+    onreset index := UInt<3>(0)
     wire elts : UInt<4>[7]
     elts[0] := UInt<4>(0)
     elts[1] := UInt<4>(4)
@@ -18,16 +20,16 @@ circuit MemorySearch :
     elts[5] := UInt<4>(5)
     elts[6] := UInt<4>(13)
     infer accessor elt = elts[index]
-    node T_35 = bit-not(en)
+    node T_35 = not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
-    node T_38 = bit-or(T_36, T_37)
-    node end = bit-and(T_35, T_38)
+    node T_38 = or(T_36, T_37)
+    node end = and(T_35, T_38)
     when en : index := UInt<1>(0)
     else : 
-      node T_39 = bit-not(end)
+      node T_39 = not(end)
       when T_39 : 
-        node T_40 = add-wrap(index, UInt<1>(1))
+        node T_40 = addw(index, UInt<1>(1))
         index := T_40
     done := end
     address := index
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 04c119a1..2fde69f3 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = add-wrap(in, UInt<1>(1))
+    node T_33 = addw(in, UInt<1>(1))
     out := T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_34 = add-wrap(in, UInt<1>(1))
+    node T_34 = addw(in, UInt<1>(1))
     out := T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 14db8769..1552e959 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -24,6 +24,6 @@ circuit Mul :
     tbl[14] := UInt<4>(6)
     tbl[15] := UInt<4>(9)
     node T_42 = shl(x, 2)
-    node T_43 = bit-or(T_42, y)
+    node T_43 = or(T_42, y)
     infer accessor T_44 = tbl[T_43]
     z := T_44
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index d24bc383..cca645d1 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,11 +3,13 @@
 circuit RegisterVecShift : 
   module RegisterVecShift : 
     input load : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4]
+    reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] := UInt<4>(0)
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 4bce2bd4..5bbec6d2 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -5,31 +5,33 @@ circuit Stack :
     input push : UInt<1>
     input pop : UInt<1>
     input en : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    cmem stack_mem : UInt<32>[16]
-    reg sp : UInt<5>
-    on-reset sp := UInt<5>(0)
-    reg out : UInt<32>
-    on-reset out := UInt<32>(0)
+    cmem stack_mem : UInt<32>[16],clk
+    reg sp : UInt<5>,clk,reset
+    onreset sp := UInt<5>(0)
+    reg out : UInt<32>,clk,reset
+    onreset out := UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
-      node T_31 = bit-and(push, T_30)
+      node T_31 = and(push, T_30)
       when T_31 : 
         infer accessor T_32 = stack_mem[sp]
         T_32 := dataIn
-        node T_33 = add-wrap(sp, UInt<1>(1))
+        node T_33 = addw(sp, UInt<1>(1))
         sp := T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
-        node T_35 = bit-and(pop, T_34)
+        node T_35 = and(pop, T_34)
         when T_35 : 
-          node T_36 = sub-wrap(sp, UInt<1>(1))
+          node T_36 = subw(sp, UInt<1>(1))
           sp := T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
-        node T_38 = sub-wrap(sp, UInt<1>(1))
+        node T_38 = subw(sp, UInt<1>(1))
         infer accessor T_39 = stack_mem[T_38]
         out := T_39
     dataOut := out
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index f315aaa9..b916e0f0 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -4,10 +4,11 @@ circuit Tbl :
   module Tbl : 
     input i : UInt<16>
     input d : UInt<16>
+    input clk : Clock
     output o : UInt<16>
     input we : UInt<1>
     
-    cmem m : UInt<10>[256]
+    cmem m : UInt<10>[256],clk
     o := UInt<1>(0)
     when we : 
       infer accessor T_13 = m[i]
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 10784964..0f4bf941 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -5,9 +5,11 @@ circuit VendingMachine :
     output valid : UInt<1>
     input nickel : UInt<1>
     input dime : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     
-    reg state : UInt<3>
-    on-reset state := UInt<3>(0)
+    reg state : UInt<3>,clk,reset
+    onreset state := UInt<3>(0)
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
       when nickel : state := UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index a0c1e10a..f3f12017 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -3,19 +3,21 @@
 circuit GCD : 
   module GCD : 
     input e : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output z : UInt<16>
     output v : UInt<1>
     input a : UInt<16>
     input b : UInt<16>
     
-    reg x : UInt<16>
-    reg y : UInt<16>
+    reg x : UInt<16>,clk,reset
+    reg y : UInt<16>,clk,reset
     node T_17 = gt(x, y)
     when T_17 : 
-      node T_18 = sub-wrap(x, y)
+      node T_18 = subw(x, y)
       x := T_18
     else : 
-      node T_19 = sub-wrap(y, x)
+      node T_19 = subw(y, x)
       y := T_19
     when e : 
       x := a
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 21030448..fda21820 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
+; CHECK: Done!
 circuit Risc : 
   module Risc : 
     output out : UInt<32>
@@ -8,11 +8,13 @@ circuit Risc :
     input isWr : UInt<1>
     input wrAddr : UInt<8>
     input wrData : UInt<32>
+    input clk : Clock
+    input reset : UInt<1>
     
-    cmem file : UInt<32>[256]
-    cmem code : UInt<32>[256]
-    reg pc : UInt<8>
-    on-reset pc := UInt<8>(0)
+    cmem file : UInt<32>[256],clk
+    cmem code : UInt<32>[256],clk
+    reg pc : UInt<8>,clk,reset
+    onreset pc := UInt<8>(0)
     infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
@@ -35,12 +37,12 @@ circuit Risc :
       else : 
         node T_56 = eq(UInt<1>(0), op)
         when T_56 : 
-          node T_57 = add-wrap(ra, rb)
+          node T_57 = addw(ra, rb)
           rc := T_57
         node T_58 = eq(UInt<1>(1), op)
         when T_58 : 
           node T_59 = shl(rai, 8)
-          node T_60 = bit-or(T_59, rbi)
+          node T_60 = or(T_59, rbi)
           rc := T_60
         out := rc
         node T_61 = eq(rci, UInt<8>(255))
@@ -48,5 +50,5 @@ circuit Risc :
         else : 
           infer accessor T_62 = file[rci]
           T_62 := rc
-        node T_63 = add-wrap(pc, UInt<1>(1))
+        node T_63 = addw(pc, UInt<1>(1))
         pc := T_63
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index cede6f43..4858fafb 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -3,26 +3,27 @@
 ; CHECK: Lower To Ground
 circuit top :
    module top :
+      input clk : Clock
       wire i : UInt<2>
       wire j : UInt<32>
 
       wire a : UInt<32>[4]
-      ; CHECK: wire a$0 : UInt<32>
-      ; CHECK: wire a$1 : UInt<32>
-      ; CHECK: wire a$2 : UInt<32>
-      ; CHECK: wire a$3 : UInt<32>
+      ; CHECK: wire a_0 : UInt<32>
+      ; CHECK: wire a_1 : UInt<32>
+      ; CHECK: wire a_2 : UInt<32>
+      ; CHECK: wire a_3 : UInt<32>
 
       infer accessor b = a[i]
       ; CHECK: wire b : UInt<32>
-      ; CHECK: b := (a$0 a$1 a$2 a$3)[i]
+      ; CHECK: b := (a_0 a_1 a_2 a_3)[i]
       j := b
 
       infer accessor c = a[i]
       ; CHECK: wire c : UInt<32>
-      ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
+      ; CHECK: (a_0 a_1 a_2 a_3)[i] := c
       c := j
       
-      cmem p : UInt<32>[4]
+      cmem p : UInt<32>[4],clk
       infer accessor t = p[i]
       ; CHECK: accessor t = p[i]
       j := t
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index e71e9104..ebf81093 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
       wire j : { x : UInt<32>, flip y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a$0$x : UInt<32>
-      ; CHECK: wire a$0$y : UInt<32>
-      ; CHECK: wire a$1$x : UInt<32>
-      ; CHECK: wire a$1$y : UInt<32>
+      ; CHECK: wire a_0_x : UInt<32>
+      ; CHECK: wire a_0_y : UInt<32>
+      ; CHECK: wire a_1_x : UInt<32>
+      ; CHECK: wire a_1_y : UInt<32>
 
       infer accessor b = a[i]
-      ; CHECK: wire b$x : UInt<32>
-      ; CHECK: wire b$y : UInt<32>
-      ; CHECK: b$x := (a$0$x a$1$x)[i]
-      ; CHECK: (a$0$y a$1$y)[i] := b$y
+      ; CHECK: wire b_x : UInt<32>
+      ; CHECK: wire b_y : UInt<32>
+      ; CHECK: b_x := (a_0_x a_1_x)[i]
+      ; CHECK: (a_0_y a_1_y)[i] := b_y
       j := b
       
       infer accessor c = a[i]
-      ; CHECK: wire c$x : UInt<32>
-      ; CHECK: wire c$y : UInt<32>
-      ; CHECK: (a$0$x a$1$x)[i] := c$x
-      ; CHECK: c$y := (a$0$y a$1$y)[i]
+      ; CHECK: wire c_x : UInt<32>
+      ; CHECK: wire c_y : UInt<32>
+      ; CHECK: (a_0_x a_1_x)[i] := c_x
+      ; CHECK: c_y := (a_0_y a_1_y)[i]
       c := j
 
 
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index c0acfecd..7c11cbc5 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -17,37 +17,34 @@ circuit top :
 ;CHECK: Lower To Ground
 ;CHECK: circuit top :
 ;CHECK:    module m :
-;CHECK:       input a$x : UInt<5>
-;CHECK:       output a$y : SInt<5>
-;CHECK:       output b$x : UInt<5>
-;CHECK:       input b$y : SInt<5>
-;CHECK:       input reset : UInt<1>
+;CHECK:       input a_x : UInt<5>
+;CHECK:       output a_y : SInt<5>
+;CHECK:       output b_x : UInt<5>
+;CHECK:       input b_y : SInt<5>
 ;CHECK:    module top :
-;CHECK:       input c$x$0 : UInt<5>
-;CHECK:       input c$x$1 : UInt<5>
-;CHECK:       input c$x$2 : UInt<5>
-;CHECK:       input c$x$3 : UInt<5>
-;CHECK:       input c$x$4 : UInt<5>
-;CHECK:       output c$y$x$0 : UInt<5>
-;CHECK:       output c$y$x$1 : UInt<5>
-;CHECK:       output c$y$x$2 : UInt<5>
-;CHECK:       input c$y$y : SInt<5>
-;CHECK:       input reset : UInt<1>
-;CHECK:       wire a$x : UInt<5>
-;CHECK:       wire a$y : SInt<5>
-;CHECK:       wire b$x : UInt<5>
-;CHECK:       wire b$y : SInt<5>
-;CHECK:       a$x := b$x
-;CHECK:       b$y := a$y
+;CHECK:       input c_x_0 : UInt<5>
+;CHECK:       input c_x_1 : UInt<5>
+;CHECK:       input c_x_2 : UInt<5>
+;CHECK:       input c_x_3 : UInt<5>
+;CHECK:       input c_x_4 : UInt<5>
+;CHECK:       output c_y_x_0 : UInt<5>
+;CHECK:       output c_y_x_1 : UInt<5>
+;CHECK:       output c_y_x_2 : UInt<5>
+;CHECK:       input c_y_y : SInt<5>
+;CHECK:       wire a_x : UInt<5>
+;CHECK:       wire a_y : SInt<5>
+;CHECK:       wire b_x : UInt<5>
+;CHECK:       wire b_y : SInt<5>
+;CHECK:       a_x := b_x
+;CHECK:       b_y := a_y
 ;CHECK:       inst i of m
-;CHECK:       i.reset := reset
-;CHECK:       i.a$x := a$x
-;CHECK:       a$y := i.a$y
-;CHECK:       b$x := i.b$x
-;CHECK:       i.b$y := b$y
-;CHECK:       wire d$0 : UInt<5>
-;CHECK:       wire d$1 : UInt<5>
-;CHECK:       wire d$2 : UInt<5>
-;CHECK:       wire d$3 : UInt<5>
-;CHECK:       wire d$4 : UInt<5>
+;CHECK:       i.a_x := a_x
+;CHECK:       a_y := i.a_y
+;CHECK:       b_x := i.b_x
+;CHECK:       i.b_y := b_y
+;CHECK:       wire d_0 : UInt<5>
+;CHECK:       wire d_1 : UInt<5>
+;CHECK:       wire d_2 : UInt<5>
+;CHECK:       wire d_3 : UInt<5>
+;CHECK:       wire d_4 : UInt<5>
 ;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 420c3c7c..57c68398 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -27,9 +27,9 @@ circuit top :
 
 ; CHECK: Lower To Ground
 
-; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
-; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m>
+; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index a2eb1215..1f38d10e 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -3,34 +3,35 @@
 ; CHECK: Lower To Ground
 circuit top :
    module top :
+      input clk : Clock
       wire i : UInt
       wire j : { x : UInt<32>, flip y : UInt<32> }
       wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a$0$x : UInt<32>
-      ; CHECK: wire a$0$y : UInt<32>
-      ; CHECK: wire a$1$x : UInt<32>
-      ; CHECK: wire a$1$y : UInt<32>
+      ; CHECK: wire a_0_x : UInt<32>
+      ; CHECK: wire a_0_y : UInt<32>
+      ; CHECK: wire a_1_x : UInt<32>
+      ; CHECK: wire a_1_y : UInt<32>
 
       infer accessor b = a[i]
-      ; CHECK: wire b$x : UInt<32>
-      ; CHECK: wire b$y : UInt<32>
-      ; CHECK: b$x := (a$0$x a$1$x)[i]
-      ; CHECK: (a$0$y a$1$y)[i] := b$y
+      ; CHECK: wire b_x : UInt<32>
+      ; CHECK: wire b_y : UInt<32>
+      ; CHECK: b_x := (a_0_x a_1_x)[i]
+      ; CHECK: (a_0_y a_1_y)[i] := b_y
       j := b
 
-      cmem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: cmem m$x : UInt<32>[2]
-      ; CHECK: cmem m$y : UInt<32>[2]
+      cmem m : { x : UInt<32>, y : UInt<32> }[2],clk
+      ; CHECK: cmem m_x : UInt<32>[2]
+      ; CHECK: cmem m_y : UInt<32>[2]
 
       infer accessor c = m[i] ; MALE
-      ; CHECK: accessor c$x = m$x[i]
-      ; CHECK: accessor c$y = m$y[i]
+      ; CHECK: accessor c_x = m_x[i]
+      ; CHECK: accessor c_y = m_y[i]
 
       c := k
-      ; CHECK: c$x := k$x
-      ; CHECK: c$y := k$y
+      ; CHECK: c_x := k_x
+      ; CHECK: c_y := k_y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index a3c4f0ae..b045aadc 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -5,17 +5,19 @@
             module top :
                input a : UInt<16>
                input b : UInt<16>
+               input clk : Clock
+               input reset : UInt<1>
                output z : UInt
 
-               reg r1 : { x : UInt, flip y : SInt }
+               reg r1 : { x : UInt, flip y : SInt },clk,reset
                wire q : { x : UInt, flip y : SInt }
-               on-reset r1 := q    
+               onreset r1 := q    
 
-      ; CHECK: reg r1$x : UInt
-      ; CHECK: reg r1$y : SInt
-      ; CHECK: wire q$x : UInt
-      ; CHECK: wire q$y : SInt
-      ; CHECK: on-reset r1$x := q$x
-      ; CHECK: on-reset q$y := r1$y   
+      ; CHECK: reg r1_x : UInt
+      ; CHECK: reg r1_y : SInt
+      ; CHECK: wire q_x : UInt
+      ; CHECK: wire q_y : SInt
+      ; CHECK: onreset r1_x := q_x
+      ; CHECK: onreset q_y := r1_y   
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir
deleted file mode 100644
index 97d32397..00000000
--- a/test/passes/make-explicit-reset/mix-reset.fir
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
-
-; CHECK: Make Explicit Reset
-circuit top :
-   module A :
-      ;CHECK: input reset : UInt<1>
-      input x : UInt<16>
-      output y : UInt<16>
-      inst b of B
-      ;CHECK: b.reset := reset
-   module B :
-      input reset : UInt<1>
-      ;CHECK: input reset : UInt<1>
-      input x : UInt<16>
-      output y : UInt<16>
-      inst c of C
-      ;CHECK: c.reset := reset
-   module C :
-      ;CHECK: input reset : UInt<1>
-      input a : UInt<16>
-      input b : UInt<16>
-   module top :
-      ;CHECK: input reset : UInt<1>
-      input a : UInt<16>
-      input b : UInt<16>
-      output z : UInt<1>
-      inst x of A
-      ;CHECK: x.reset := reset
-;CHECK: Finished Make Explicit Reset
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 6fbaad85..da15cb78 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -6,19 +6,21 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z := sub-wrap(x, y)
-      ;CHECK: z@<g:f> := sub-wrap(x@<g:m>, y@<g:m>)
+      z := subw(x, y)
+      ;CHECK: z@<g:f> := subw(x@<g:m>, y@<g:m>)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
 ; CHECK: reg x : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
       ;CHECK: when gt(x@<g:m>, y@<g:m>) :
          inst s of subtracter
@@ -40,12 +42,16 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
       i.b := b
+      i.clk := clk
+      i.reset := reset
       i.e := UInt(1)
       z := i.z
 
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 383c2a31..354545fb 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -3,8 +3,10 @@
 ;CHECK: Lower To Ground
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire w : { flip x : UInt<10>}
-      reg r : { flip x : UInt<10>}
+      reg r : { flip x : UInt<10>},clk,reset
       w := r     ; CHECK r$x := w$x
       w.x := r.x ; CHECK w$x := r$x
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index 341910d4..cd02a463 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -6,18 +6,20 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z := sub-wrap(x, y)
-      ;CHECK: z@<k:port> := sub-wrap(x@<k:port>, y@<k:port>)
+      z := subw(x, y)
+      ;CHECK: z@<k:port> := subw(x@<k:port>, y@<k:port>)
    module gcd :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -37,11 +39,15 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
       ;CHECK: inst i of gcd@<k:module>
       i.a := a
       i.b := b
+      i.clk := clk
+      i.reset := reset
       i.e := UInt(1)
       z := i.z
       ;CHECK: z@<k:port> := i@<k:inst>.z
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index 5af83202..fc49335c 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,10 +35,14 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       output z : UInt
       inst i of gcd
+      i.clk := clk
+      i.reset := reset
       i.a := a
       i.b := b
       i.e := UInt(1)
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
index 3d5ea30f..84998989 100644
--- a/test/passes/to-flo/gcd.fir
+++ b/test/passes/to-flo/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -35,8 +37,12 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
+      i.clk := clk
+      i.reset := reset
       i.a := a
       i.b := b
       i.e := UInt(1)
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
index 23a2d4f5..9b8732a6 100644
--- a/test/passes/to-verilog/gcd.fir
+++ b/test/passes/to-verilog/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -35,11 +37,14 @@ circuit top :
    module top :
       input a : UInt<16>
       input b : UInt<16>
+      input clk : Clock
+      input reset : UInt<1>
       output z : UInt
       inst i of gcd
+      i.clk := clk
+      i.reset := reset
       i.a := a
       i.b := b
       i.e := UInt(1)
       z := i.z
 ;CHECK: Done!
-