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authorAdam Izraelevitz2015-07-28 13:29:55 -0700
committerAdam Izraelevitz2015-07-28 13:29:55 -0700
commit0c7aca561aef907314b0d9c9737fcea04ae6ce82 (patch)
tree1b5a4da96413bd34d6b5e05ed2cbb2312d1a4b1d /Makefile
parent69e4bc2c4f4e7c2940633f12a40a5550205eb75e (diff)
Integrated bigint. Mostly works, but getting "cast" error for make Test.
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/Makefile b/Makefile
index 6eda3cc3..3fb491c4 100644
--- a/Makefile
+++ b/Makefile
@@ -48,12 +48,12 @@ clean:
riscv:
cd $(test_dir)/riscv-mini && lit -v . --path=$(root_dir)/utils/bin/
-units = ALUTop Datapath Control Core
+units = ALUTop Datapath Control Core Test
v = $(addsuffix .fir.v, $(units))
$(units): % :
- firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c
- scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
+ firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c > test/chisel3/$*.fir.out
+ #scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
done:
say "done"