Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works

1 files changed, 6 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 07184181..1bacf104 100644
--- a/Makefile
+++ b/Makefile
@@ -42,6 +42,12 @@ clean:
 	rm -f $(test_dir)/*/*/*.out
 	rm -f $(test_dir)/*/*.out
 
+riscv:
+	cd $(test_dir)/riscv-mini && lit -v . --path=$(root_dir)/utils/bin/
+
+push:
+	scp test/riscv-mini/*.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src
+
 done:
 	say "done"