From f8f9de58dbba5e53193246a5fd2145dfe6537e10 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 10:41:27 -0700
Subject: Added sequential/combinational memories. Started debugging verilog
 backend. Added Long support so UInt(LARGENUMBER) works

---
 Makefile | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 07184181..1bacf104 100644
--- a/Makefile
+++ b/Makefile
@@ -42,6 +42,12 @@ clean:
 	rm -f $(test_dir)/*/*/*.out
 	rm -f $(test_dir)/*/*.out
 
+riscv:
+	cd $(test_dir)/riscv-mini && lit -v . --path=$(root_dir)/utils/bin/
+
+push:
+	scp test/riscv-mini/*.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src
+
 done:
 	say "done"
 
-- 
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