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2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-28[Testing] Clean up SimpleTransformSpec execute methodsJack Koenig
This makes it more concise to write tests
2017-06-28[Testing] Have SimpleTransformSpec mix in FirrtlMatchersJack Koenig
Gives all transform specs access to useful utilities (like dontTouch). Deletes some duplicate code. Parsing mode UseInfo is fine for everything, only matters if the test actually uses info.
2017-06-28Merge pull request #615 from freechipsproject/remove-resetJack Koenig
Remove reset and fix bug in register update Verilog emission
2017-06-27Add RemoveReset transform to replace register reset with a MuxJack Koenig
2017-06-27Emitting reg update mux tree, only walk netlist for wires and nodesJack Koenig
Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update.
2017-06-26Add support for wires in ConstPropJack Koenig
This requires a quick second pass to back propagate constant wires but the QoR win is substantial. We also only need to count back propagations in determining whether to run ConstProp again which shaves off an iteration in the common case.
2017-06-26Speed up ConstProp by doing ConstProp before recording nodeJack Koenig
Similar to #543
2017-06-21Add --no-dce command-line option to skip DCEJack Koenig
2017-06-13Replace IsInvalids on LowForm with connection to zeroJack Koenig
2017-06-13Canonicalize spacing in RemoveValidIfJack Koenig
2017-06-13Make ExpandWhens delete 'is invalid' for attached Analog componentsJack Koenig
Also add tests for what should happen to 'is invalid' in ExpandWhens Fixes #606
2017-06-13Style changes to ExpandWhensSpecJack Koenig
2017-06-12Add option to disable combinational loop detectionJack Koenig
Resolves #600
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Change CheckCombLoops to a TransformJack Koenig
2017-06-12Fixes a typo in the verilog `elsif code generation (#603)Shreesha Srinath
2017-06-08Update travis button for new organization (#602)Colin Schmidt
2017-06-06Display the total time firrtl took to compile (#599)Colin Schmidt
* Display the total time firrtl took to compile * Switch timing print out to error(aka default)
2017-05-30Change base of randomization values to _RAND instead of _GENJack Koenig
2017-05-30Add some comments to `endifJack Koenig
Makes Verilog more readable to both humans and scripts
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
* Update dependencies and JavaConverters for Scala 2.12 * Bump Scala (and library) version(s). * replace "error" with "Utils.error"; bump Scala version to 2.11.11
2017-05-25Fix performance bug in DCE (#596)Jack Koenig
We walked the whole set of vertices for every dont touch
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
We were recursing on Types of Expressions which not only is super inefficient (especially since we are already calling InferTypes afterward), but also duplicates each of the Type objects that need changing.
2017-05-19Delete black_box_verilog_files.f if we aren't going to create it - fixes ↵Jim Lawson
#504 (#551)
2017-05-18Bump scopt for prettier option parsing (#546)Schuyler Eldridge
Scopt 3.5.0 adds (subjectively) sane two-column output of option parsing help text which it enables by default.
2017-05-18Upgrade Logging facility (#488)Chick Markley
* Upgrade Logging facility Make thread-safe Make logging by package name work Use caching of class names to level for performance Make some tests to show this working * quick fix for dynamic logging variable * A number of changes based on Adam's suggestions Default LoggerState But there is an invoke method now to handle threading issues. This should be propagated to other projects Driver.execute methods * Add built-in support for string capture of Logging * Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible. * A couple style fixes Comment and privatize Logger state * Name and save string buffers used for logging * Fix default logging state setting Fix logging test, did not have change to command argument * comment out logging in InlineInstanceTests * Changed invoke to makeScope Nested makeScopes share same state object Removed earlier named string buffer implementation * Better name for captor get data * Add trace tests to make sure it works too * Fix call into logger settings
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
Fixes #589
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
* Bugfix: pad is max(width,const) during constprop * Fixed max syntax
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation. Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed. This transform preserves deduplication. All instances of a given DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Fix typo in ExecutionOptionsManager comment (#520)Colin Schmidt
Now you should be able to copy paste the example code :)
2017-05-10Update rename2 (#478)Adam Izraelevitz
* Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
Remove infix notation on calls with side effects.
2017-05-03Add test for source locators on multi-line reset registers (#554)Jack Koenig
Test for #468
2017-04-28Add info on reset block lines to ANTLR grammar (#468)Albert Magyar
Fixes #409
2017-04-20move circuit dumping to trace so debug gives annos only (#524)Colin Schmidt
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
2017-04-13Speed up CSE by doing CSE on node expression before recording the node (#543)Jack Koenig
This means CSE need only be run once to get same QOR and prevents pathological cases. Fixes #448
2017-04-04DecorateMems should not delete annoations (#523)Colin Schmidt
2017-04-03Change implicit value classes to prefix with _ (#522)Adam Izraelevitz
Fixes bug where arbitrary expressions, if called with .expr, return the same expression.
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-30Make force-append-anno-file work. Fixes #515 (#516)Jack Koenig
2017-03-30Change findSCCs to iterative implementation (#513)Albert Magyar
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-23Add TargetDirAnnotation to give transforms access (#503)Jack Koenig
Also add GlobalCircuitAnnotation for creating similar annotations
2017-03-22Throw different error message for missing emitannoAdam Izraelevitz